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Sensor square wave input
Robbe is right to put this within a clocked process. This code, however, will not perform as you would expect. This is what happens: When the first condition is true, the second will also be true! This means that the variable HUM1 will be set and immediately cleared since a process handles... -
Some support for VHDL project
Hi borissofia, The component looks like an OR function. I would use a simple std_logic signal to connect COMP with TRIG. Bert -
VHDL latches
Hi Kushan, Use a flip-flop. That's simply the best way to do it. Bert -
What's wrong witht that code?
The problem is the names you are using. Your input is called "Switches" and later on you use the name "switch". I've changed it in the code below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.numeric_std.all; entity... -
Image Processing with DE2 and TRDB_DC2
Hi Chrisab508, Maybe it's a good idea to start with something more simple? External RAM memories are quite complex in VHDL. If I were you, I would start with an introduction to VHDL. They can be found on the internet. Bert -
OBUFDS or OBUFDS_LVDS ?? plz help me about differential signal
Hi Jckseiko, You can just use the OBUFDS (Output buffer differantial). Use it as followes: entity transmitter is port ( clock : in std_logic; reset : in std_logic; -- system reset Data_out_p : out std_logic; -- differential data output Data_out_n : out std_logic --... -
What's wrong witht that code?
Hi Jackseiko, In your IF statement you test the condition as followes: if( switch(0)<='1') then This must be: if( switch(0)='1') then <= is for assigning and = is for testing. Bert -
unused inputs.
Hi Faitie, The problem lies in you IF statement. It's important to use the right TAB settings in you editor, then you would see the error easily. I'll show you: ... if S1 = '1' then aan2 <= '1'; enable(0) <= '0'; enable(1) <= '1'; enable(2) <= '1'... -
i can't activate a signal after 12 cycles. pls help
Hi Tecton, The problem is, that you are missing the following library: ieee.std_logic_unsigned.all What you are doing with the clock signal is very very strange. You've made a clock enable, but you've put the if statement before the clock if statement? I've rewritten your code. There are... -
VHDL - Driving 1 bit off 2 clocks
Hi Snooks, You should use flags between processes. The implementation of such inter process communication, depents very much on the specific demands. I wrote an example below, to give you an idea of how to do this. [codewrite data process] process(clk) is begin if( clk'event AND clk =... -
VHDL state machine timing problems
Hi PouriaPouria, What do you mean by "exits"? Maby you should post your VHDL code, then it's better to understand for us. Bye... -
state machine
Hi Brian, You need to close the first case statement and open the second one: ... when "001" -- door open? end case; -- This is a different type!!! case Sreg0 is when S3 => ... Bye... -
Signal xx cannot be synthesized, bad synchronous description
Hi thehell, The problem is that you assign signals both in and out of the synchronous part of your design. If you assign signals (C is not the only one) synchronous in an if statement with a clock (IF (clk'event AND clk='1')), the tools will create a register. It will not know what to create... -
signal problem
Hi, First of all: Why is it necessary that you obtain the signal immediately? And second: If you want to do it without delay, you need to remove all register in that signal, but be very carefull with this because of timing issues!!! -
Instantiating in VHDL
Hi MrAndersan, Could you post the entire code? Also your fulladder code? -
How to design a microcontroller using VHDL?
Didn't the VHDL code for the processor came with a testbench? -
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How to design a microcontroller using VHDL?
Hi Nyep, A soft-core processor is a microprocessor which can be implemented into the existing technology in the FPGA. This means that it uses the same components as the ones you use while developing VHDL, because the core itself is written in VHDL. You can find a lot of information at the... -
Tri-State Signals
Hi Trump110, The signal REG_0_HOLD is multi driven, because you assign a value to REG_0_HOLD(2) and REG_0_HOLD(3) in both processes above. Another problem with REG_0_HOLD is, that you haven't assigned a value to it at states 0-14. This will cause undefined values and probrably will produce bad...
