Instantiating in VHDL

[MrAndersan]

Hello all, I am trying to create a signed array multiplier using combinational logic on Xilinx's free ISE 9.2i webpack. First off, one strange issue, the program won't even let me synthesize any verilog modules. So I've been coding in VHDL, which is ok, but my Professor's lecture notes are in Verilog, and I'm having some problems converting the instantiation code.

Here is what I have:

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity five_bit_full_adder is
port(clk: IN STD_LOGIC;
start: IN STD_LOGIC;
done: OUT STD_LOGIC);


end five_bit_full_adder;

architecture five_bit_full_adder of fulladder is
component fulladder
port(clk: IN STD_LOGIC;
a: IN STD_LOGIC;
b: IN STD_LOGIC;
cin: IN STD_LOGIC;
sum: OUT STD_LOGIC;
cout: OUT STD_LOGIC);
end component;
begin
-- full adder instantiation
fulladder1: fulladder port map(a,b,cin,clk,cout,sum);
process
begin
wait until clk = '1';
if start = '1' then
done <= '1';

end if;
end process;
done <= '1';

end five_bit_full_adder;


All I want to do is test instantiating the fulladder. But I can't even do that, I'm getting so archaic error:

line 54:Component 'fulladder' has been instantiated recursively 64 times. Use "set -recursion_iteration_limit XX" to iterate more.

Can anyone give me some detailed pointers of what I am doing wrong and perhaps code to help me along? Thanks

 

[BertVhdl]

Hi MrAndersan,

Could you post the entire code? Also your fulladder code?