Hello guys, im starting to learn VHDL programming, i have a manual, i´m using MODELSIM, and i write the code that appears in the manual but it finds an error!!, can u help me?
the code is:
entity adder is
port(a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
end adder;
architecture rtl of adder is
begin
sum <= (a xor b) xor cin;
cout <= (a and b) or ((a xor b) and cin);
end rtl;
I can´t remember the error, but it´s a very simple code.
I hope u can help me
the code is:
entity adder is
port(a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
end adder;
architecture rtl of adder is
begin
sum <= (a xor b) xor cin;
cout <= (a and b) or ((a xor b) and cin);
end rtl;
I can´t remember the error, but it´s a very simple code.
I hope u can help me