What's wrong witht that code?

[jackseiko]

someone please tell me what's the problem with the code? TAI

------------------------------------------------------------

entity switches is
port(
clock : in std_logic;
Switches : in std_logic_vector ( 3 downto 0);
output: out std_logic_vector (7 downto 0) );
end switches;

architecture switches of switches is

begin
process(clock, switches)
begin
if(rising_edge(clock)) then
if( switch(0)<='1') then
output <="00000001" ;
elsif (switch(1)<='1') then
output <="00000010" ;
elsif (switch(2) <='1') then
output <="00000100" ;
elsif (switch(3) <='1') then
output <="00001000" ;
end if;
end if;
end process;

end switches;

 

[BertVhdl]

Hi Jackseiko,

In your IF statement you test the condition as followes:
if( switch(0)<='1') then

This must be:
if( switch(0)='1') then

<= is for assigning and = is for testing.

Bert

 

[jackseiko]

Hi Bert,

thank you so much for your reply, I have made the change, but I still encounter with the same problem which is;

ERROR:HDLParsers:808 - "C:/XilinX92i/transmitter/switches.vhd" Line 24. = can not have such operands in this context.

I couldn't get what's the problem with that code. I just want to the code perform that;
when Switch0 is '1', output <="00000001"
when Switch1 is '1', output <="00000010"
when Switch2 is '1', output <="00000100"
when Switch3 is '1', output <="00001000"

I'd be grateful if u tell me a solution, thanks in advance
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;



entity switches is
port(
clock : in std_logic;
Switches : in std_logic_vector ( 3 downto 0);
output: out std_logic_vector (7 downto 0) );
end switches;

architecture switches of switches is

begin
process(clock, switches)
begin
if(rising_edge(clock)) then
if( switch(0)='1') then
output <= "00000001" ;
elsif (switch(1)='1') then
output <= "00000010" ;
elsif (switch(2) ='1') then
output <= "00000100" ;
elsif (switch(3) ='1') then
output <= "00001000" ;
end if;
end if;
end process;

end switches;

 

[BertVhdl]

The problem is the names you are using.

Your input is called "Switches" and later on you use the name "switch".

I've changed it in the code below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;



entity switches is
  port(
    clock     : in  std_logic;
    Switches  : in  std_logic_vector(3 downto 0);
    output    : out std_logic_vector(7 downto 0) 
  );
end switches;

architecture switches of switches is
begin
  
  process(clock, switches) 
  begin
    if(rising_edge(clock)) then
      if( Switches(0)='1') then
        output <= "00000001" ;
      elsif (Switches(1)='1') then
        output <= "00000010" ;        
      elsif (Switches(2) ='1') then
        output <= "00000100" ;
      elsif (Switches(3) ='1') then
        output <= "00001000" ;    
      end if;
    end if;
  end process;
                
end switches;