Some support for VHDL project

[borissofia]

Hi Folks,

I have to model following device (

http://alfist.hit.bg/task.jpg)

via VHDL.

First picture in attachment is taks seccond is my current result.


CNT – 8 bit counter up form CLK fornt with asinchronus zero input.

COMP – comparator for 2 8 bits digits.

TRIG – D-trigger, synchronized via up CLK front and asynchronous form zero in.

REG – 8 bit parallel register synchronized by up WR front and and asynchronous form zero in.

Questions:

What is the role of device in red rectangle?

what kind of signal wire should i use to connect COMP with TRIG.

Here is the source of Top level board:

library ieee; -- top level circuit
use ieee.std_logic_1164.all;
use work.all;

entity comb_ckt is
port( input1: in std_logic_vector(7 downto 0);
output: out std_logic
);
end comb_ckt;

architecture struct of comb_ckt is

component Comparator is

generic(n: natural :=2);
port( A: in std_logic_vector(7 downto 0);
B: in std_logic_vector(7 downto 0);
less: out std_logic;
equal: out std_logic;
greater: out std_logic
);
end component;


component REG is port (
d: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
q: out std_logic_vector(7 downto 0));
end component;

component counter is

generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;

component TRIG is port (
d: in std_logic;
q: out std_logic;
clk: in std_logic;
rst: in std_logic
);
end component;

--component Driver is
--port( x: in std_logic_vector(7 downto 0);
--F: out std_logic
--);
--end component;



signal wire: std_logic_vector(7 downto 0); -- signal just like wire
signal wire_conn_REG_COMP: std_logic_vector(7 downto 0); -- signal just like wire
signal wire_conn_CNT_REG: std_logic_vector(7 downto 0); -- signal just like wire
signal wire_CLR_CONN_CNT_REG: std_logic;
signal wire_CLR_CONN_COMP_TRIG: std_logic;
signal wire_CLR_DRV_TRIG: std_logic;
--Dummy Wares

signal wire_001: std_logic; -- signal just like wire
signal wire_002: std_logic; -- signal just like wire
signal wire_003: std_logic; -- signal just like wire

signal wire_004: std_logic; -- signal just like wire
signal wire_005: std_logic; -- signal just like wire
signal wire_006: std_logic; -- signal just like wire
signal wire_conn_COMP_B: std_logic_vector(7 downto 0);

signal wire_0077: std_logic; -- signal just like wire

begin

-- use sign "=>" to clarify the pin mapping

REG01: REG port map (d=>input1, q=>wire_conn_REG_COMP, clk=> wire_001, rst=>wire_CLR_CONN_CNT_REG, ena=>wire_003);
COMP01: Comparator port map (A=>wire_conn_REG_COMP, B=>wire_conn_CNT_REG, less=>wire_CLR_CONN_COMP_TRIG, equal=>wire_0077);
CNT01: counter port map (Q=>wire_conn_CNT_REG, clear=>wire_CLR_CONN_CNT_REG);
TRG01: TRIG port map (q=>output, d=>wire_0077, clk=>wire_005, rst=>wire_CLR_DRV_TRIG );
--DRV01: Driver port map (x=>wire_conn_CNT_REG, f=>wire_CLR_DRV_TRIG);
end struct;

Here is the source of COMP:

---------------------------------------------------
-- this simple comparator has two n-bit inputs &
-- three 1-bit outputs
---------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

---------------------------------------------------

entity Comparator is

generic(n: natural :=2);
port( A: in std_logic_vector(7 downto 0);
B: in std_logic_vector(7 downto 0);
less: out std_logic;
equal: out std_logic;
greater: out std_logic
);
end Comparator;

---------------------------------------------------

architecture behv of Comparator is

begin

process(A,B)
begin
if (A<B) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then
less <= '0';
equal <= '1';
greater <= '0';
else
less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;

end behv;

---------------------------------------------------

And the source of TRIG:

library IEEE;
use IEEE.std_logic_1164.all;

entity TRIG is port (
d: in std_logic;
q: out std_logic;
clk: in std_logic;
rst: in std_logic
);
end TRIG;

architecture rtl of TRIG is

begin

process (clk, rst) begin
if rst = '0' then -- ???????? ?? ??????? ????????? ?? ????????? ??????
q <= '0';
elsif rising_edge(clk) then -- ???????? ?? ????????? ????? ?? ???????? ??????
q <= d;
end if;
end process;

end rtl;

 

[BertVhdl]

Hi borissofia,

The component looks like an OR function.

I would use a simple std_logic signal to connect COMP with TRIG.

Bert

 

[majid169]

hi
1-The component look like an automatic reset of your design.
2-std_logic

 

[borissofia]

Hi,

Many thanks for your support.

Do you have idea how to implement automatic reset module.

Some source code or advice will be appreciated.

Kind regards, Boris