ual 32

[bambino23]

hello i'm tryin to program my ual 32 bit but i'm kind having those following error.could someone help me with this issue?

regards
bambino23
code**********************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned. all;
USE WORK.mypackage.ALL;

ENTITY alu_32 IS
GENERIC (ALU_SIZE: integer := 31);
PORT (
SrcA, SrcB: IN STD_LOGIC_VECTOR (ALU_SIZE downto 0);
ALUControl : IN STD_LOGIC_VECTOR (3 downto 0);
c_out: OUT STD_LOGIC_VECTOR(ALU_SIZE downto 0);
result: INOUT STD_LOGIC_VECTOR (ALU_SIZE downto 0);
zero: out std_logic := '1'
); END alu_32 ;

ARCHITECTURE alu_32_archi OF alu_32 IS

--declarer les signaux ici. Entre autres a_invert, b_negate, operation, ...

signal a_invert, b_negate,set,less,c_in2,c_out2: std_logic;
signal operation : std_logic_vector(1 downto 0);

COMPONENT alu_1
PORT (
a, b, c_in, less : IN STD_LOGIC;
ALUControl : IN STD_LOGIC_VECTOR (3 downto 0);
c_out, result, set: OUT STD_LOGIC
); END COMPONENT;

BEGIN
a_invert <= ALUControl (3);
b_negate <= ALUControl (2);
operation <= ALUControl (1 downto 0);

--completer alu_32

alu1: alu_1 PORT MAP(SrcA(0), SrcB(0), b_negate, less, ALUControl,c_out(0), result(0), set);

FOR i IN 1 TO 31 LOOP
if (i='1')then c_in2(i)<= c_out(0);
else c_in2(i)<= c_out(i-1);
end if;
alu2: alu_1 PORT MAP(SrcA(i), SrcB(i), c_in2(i),'0',ALUControl,c_out(i), result(i), set);

END LOOP;

less <= set;

END alu_32_archi;
*****************************************
ERROR: J:/340/alu_32.vhd(50): Illegal concurrent statement.
ERROR: J:/340/alu_32.vhd(51): No feasible entries for infix op: "="
ERROR: J:/340/alu_32.vhd(51): Type error resolving infix expression.
ERROR: J:/340/alu_32.vhd(51): Illegal concurrent statement.
ERROR: J:/340/alu_32.vhd(51): Prefix of index must be an array.
ERROR: J:/340/alu_32.vhd(51): Cannot read output: c_out.
ERROR: J:/340/alu_32.vhd(52): Prefix of index must be an array.
ERROR: J:/340/alu_32.vhd(52): Cannot read output: c_out.
ERROR: J:/340/alu_32.vhd(54): The actual for parameter a must denote a static signal name.
ERROR: J:/340/alu_32.vhd(54): The actual for parameter b must denote a static signal name.
ERROR: J:/340/alu_32.vhd(54): The actual for parameter c_in must denote a static signal name.
ERROR: J:/340/alu_32.vhd(54): Prefix of index must be an array.
ERROR: J:/340/alu_32.vhd(54): Actual for formal less is not a signal.
ERROR: J:/340/alu_32.vhd(54): The actual for parameter c_out must denote a static signal name.
ERROR: J:/340/alu_32.vhd(54): The actual for parameter result must denote a static signal name.
ERROR: J:/340/alu_32.vhd(54): Value associated with a does not have a static name.
ERROR: J:/340/alu_32.vhd(54): Value associated with b does not have a static name.
ERROR: J:/340/alu_32.vhd(54): Value associated with c_in does not have a static name.
ERROR: J:/340/alu_32.vhd(54): Value associated with less does not have a static name.
ERROR: J:/340/alu_32.vhd(54): Value associated with c_out does not have a static name.
ERROR: J:/340/alu_32.vhd(54): Value associated with result does not have a static name.
ERROR: J:/340/alu_32.vhd(60): VHDL Compiler exiting

 

[BertVhdl]

Hi bambino23,

You can't use a loop statement outside a process. Use generate in stead.

Bye...