VHDL state machine timing problems

[PouriaPouria]

Hi there.

I'm trying to design a state machine to Run at 100 MHz in an Actel FPGA.

Most of my states have 6 or more exits.

My questions is how many exits can I have on one single state so that the Logic that is generated by the syntisizer dose not have a delay more then 10ns (100MHz clock).

How can I calculate this delay depending on number of exit from a single state in my state machine ???

Thank you so much for your help !!!

 

[BertVhdl]

Hi PouriaPouria,

What do you mean by "exits"?

Maby you should post your VHDL code, then it's better to understand for us.

Bye...

 

[jeandelfrigo]

PouriaPouria,

by exits is assume you mean outputs and thus you are thinking of a fan out problem.

What determines the speed of the statemachine is the logical (combinatorical) path of the next state logic.
Unless your synthesizer is already complaining (warning or error) on fan out issues. I'm not familiar with Actel devices, I use mostly Xilinx and Altera.

BertBroer is correct in asking for your VHDL code, because the way it is written effects the performance drastically. Ofcourse also the device used is of importance.
Code can be implemented succesfully and with timing on a high end FPGA but might need some tuning if you want to use it on the more low cost devices (e.g. Virtex versus Spartan)

The combinatorical part will determine the levels of logic and thus basically number of LUT delays. Excuse me again for my Xilinx terminology. Every look up table has a delay, having to put LUTs in series to create the actual function adds up these delays if the total delay for even one next state bit comes near the clock period you have a problem.

As already mentioned coding style is important, but I'll not go into this without having seen your code first.

State machine encoding is also important. One hot encoding is the fastest, but demands more flip flops. One hot encoding means every state demands a flip flop. So a 35 state FSM demands 35 flip flops. So in every state only one flip flop is active. This allows very simple state decoding and thus fewer logic to do so and thus is faster.
So try looking in the help of your implementation tool for one hot encoding or state machine implementation styles.

A second thing is try to see if there is some thing like "allow logic duplication". This is something similar where you allow a function to be replicated to split up fan out, if this is really an issue.

Try to first use all features of the device and the tools.

If this does not work than you can start by tuning the code (separate next state and output logic processes) or pipelining, but if you can avoid this it's allways better.

So please try to look for one hot encoding and/or logic duplication and if not succesful please provide the VHDL code and maybe synthesizer warnings and or errors.

Also note that timing is only definite after placement and routing.

regards

jeandelfrigo