i can't activate a signal after 12 cycles. pls help

[tecton]

hi everybody,
i'm new in vhdl and i'm trying to activate a signal after 12 cycles and then di-activate it again. for example,
start-0-0-0-0-0-0-0-0-0-0-0-0-1-0-end

i have these errors in Modelsim,
error: No feasible emtries for infix operator "+".
error: Type error resolving infix expression "+" as type ieee.std_logic_1164.std_logic_vector.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- =============== Interface Description ===============

entity COUNTER_DEC is

port (clock : in std_logic; -- positive edge
reset : in std_logic;

start : in std_logic; -- start process

done_count: out std_logic -- end of the process

);
end COUNTER_DEC;

architecture COUNTER_DEC_RTL of COUNTER_DEC is


-- =============== Signal Definition ===============

signal tmp : std_logic;
signal active : std_logic;
signal counter: std_logic_vector(3 downto 0);


-- =============== Data Movement ===============

begin

START_COUNTER: process ( clock, reset )

begin

if reset = '1' then
counter <= (others => '0');
tmp <= '0';
active <= '0';

elsif (start = '1' or active = '1') then

if clock'event and clock = '1' then
counter <= (counter + '1');
else
counter <= counter;
tmp <= tmp;
end if;
active <= active xor start;
else
counter <= "0000";
tmp <= '0';
active <= '0';
end if;

if counter = "1100" then
tmp <= '1';
counter <= "0000";
active <= '0';
else
tmp <= '0';
end if;
done_count <= tmp;

end process;

end COUNTER_DEC_RTL;

 

[BertVhdl]

Hi Tecton,

The problem is, that you are missing the following library:
ieee.std_logic_unsigned.all

What you are doing with the clock signal is very very strange. You've made a clock enable, but you've put the if statement before the clock if statement?

I've rewritten your code. There are more ways to do it, this is just an example.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

-- =============== Interface Description ===============

entity COUNTER_DEC is
	port (
		clock 		: in std_logic; -- positive edge
		reset 		: in std_logic;
		start 		: in std_logic; -- start process
		done_count	: out std_logic -- end of the process
	);
end COUNTER_DEC;

architecture COUNTER_DEC_RTL of COUNTER_DEC is


-- =============== Signal Definition ===============

signal cnt_enable 	: std_logic := '0';
signal counter_done : std_logic := '0';
signal counter		: std_logic_vector(3 downto 0) := (others=>'0');
signal start_r		: std_logic_vector(1 downto 0) := (others=>'0');

-- =============== Data Movement ===============

begin

-- Start pulse detection process
Detect_start_proc : process ( clock )

begin
	
	if ( clock'event AND clock = '1' ) then
		
		-- Detect a rising edge of the start pulse
		start_r <= start_r(0) & start;		
		
		-- Start the counter at a rising edge of start
		if ( (start_r(0) = '1') AND (start_r(1) = '0') ) then
			cnt_enable <= '1';
		-- Disable counter when it's done
		elsif ( counter_done = '1' ) then
			cnt_enable <= '0';
		-- Else remember the counter state
		else
			cnt_enable <= cnt_enable;
		end if;
				
	end if;

end process;

-- Counter process
Counter_proc: process ( clock )

begin
	
	-- Reset is not needed, because the counter is reset when no start pulse has occurred
	if ( clock'event AND clock = '1' ) then
			
		-- Count when the counter is enabled	
		if ( cnt_enable = '1' ) then
			counter <= (counter + '1');
		-- Else reset the counter
		else
			counter <= (others=>'0');
		end if;
				
	end if;

end process;

-- Counter done process
Counter_done_proc: process ( clock )

begin
	
	-- Synchronize to the rising edge
	if ( clock'event AND clock = '1' ) then
		
		-- Set the done_count signal when the counter reaches it's value
		if ( counter = "1100" ) then
			counter_done <= '1';
		else
			counter_done <= '0';
		end if;
				
	end if;

end process;

-- Output mapping
done_count <= counter_done;

end COUNTER_DEC_RTL;

I've also split up the large process into multiple small processen. By doing this, it's better managable.

I suggest you should look at the following document:

http://www.vlsi.informatik.tu-darmstadt.de/student_area/sep/hdlcode.pdf

It has some simple examples of coding style. You should firstly look on how to code proper Flip-flops. It shows examples of synchronous and asynchronous resets, clock enables and more.

Good luck!
Bert