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Recent content by jeandelfrigo
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synthesis of VHDL module
Hi, Use of variables in code intended for sysnthesis is not advised. Regards, jeandelfrigo- jeandelfrigo
- Post #2
- Forum: VHDL
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ROM addresses are read the other way around
Hello Sally000, I do not fully understand the entire system from your explanation, I'm sorry. But what I do notice is that your parallel to serial converters shifts left or MSB (=3) first , but the shift register shifts right LSB (=0) first. I would try making both the same shift direction...- jeandelfrigo
- Post #2
- Forum: VHDL
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Getting LEDs to blink in sequence
Hello Flamefury, I would just go for a shiftregister. Lets say you have 8 LEDs then make a shiftregister of 8 bit. signal LEDreg : std_logic_vector(7 downto 0) := (others => '0'); p_shiftreg : process (clk) begin if rising_edge(clk)then Ledreg(0) <= input; Ledreg(7 downto 1) <=...- jeandelfrigo
- Post #2
- Forum: VHDL
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variable used in for loop
Hello, One general remark on loops in VHDL. VHDL is a hardware description language. It reacts different from software programming languages that tell processors what to do. Even a mighty intel processor can only do one thing at a time (yes there are "behind the comma" discussion possible...- jeandelfrigo
- Post #3
- Forum: VHDL
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cache disable for vertix II pro
Hello krkrkr, It has been a while since I've used the embedded PPC in Xilinx virtexes. We used to use them as main processors, but to be honest we encountered situations where simple external microcontrollers were killing them selves because they got nuts of waiting for the PPC. They are...- jeandelfrigo
- Post #2
- Forum: VHDL
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FIFO
Hello Rosluc, Let me start by saying that you don't give a lot of information on what you want. Fifo's are very comonly used components and they exist in many flavours. A majo distinction is synchronous and asynchronous fifos. Mainly in my work I use asynchronous ones 99% of the time. A...- jeandelfrigo
- Post #2
- Forum: VHDL
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Changing PCIe cards functionality in live system
Hello, Does anyone have experience with or knowledge of re-defining the function of an FPGA based PCIe expansion card while the computer continues running. Lets take the following fictional example. A PCIe card x8 with an FPGA on board performs pheripheral functionality A for the system's CPU...- jeandelfrigo
- Thread
- Replies: 0
- Forum: PC hardware - Peripheral issues
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Basic var question
slowstart, let's get a few things straight. Delta delay is a simulation thing. It is there because 1 processor cannot do two things at the same time, where hardware can. So a processor simulator needs delta delays to emulate concurrency of hardware. Now decent hardware design is synchronous...- jeandelfrigo
- Post #2
- Forum: VHDL
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Starter question about teh rotary example
Zsolt, This is a one of many ways to do edge detection. direction: process(clk) begin if clk'event and clk='1' then delay_rotary_q1 <= rotary_q1; if rotary_q1='1' and delay_rotary_q1='0' then rotary_event <= '1'; rotary_left <= rotary_q2; else...- jeandelfrigo
- Post #2
- Forum: VHDL
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Clock Divider 100MHz to 26MHz
sunil401, Unfortunately this is not correct. What you have made here is a signal with a period of 261 kHz (100MHz /383) given that clk is 100MHz. Also the signal you made will have a period of 1/261 kHz but will only have a small duty cycle (1/100MHz on time). This is not really good if you...- jeandelfrigo
- Post #2
- Forum: VHDL
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Feedback on vhdl
tasos69, Make sure tp is also a std_logic_vector 1 downto 0. Why not just loop trough P1i to P1o (p1o <= p1i) altohough it would be better to clock it if possible.- jeandelfrigo
- Post #2
- Forum: VHDL
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How to implement a 2-way buffer based on a signal
wildchang, This is perfectly possible in VHDL. lets say the inout port is named A A_int is an internal signal containing the output values for the port A_OE is the output enable for the port A you use the following syntax to asign the output: A <= A_int when A_OE = '1' else 'Z'; This is...- jeandelfrigo
- Post #2
- Forum: VHDL
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pls help, no programing option
Nagiboy, Stick to the rules my friend. In synchronous design only one signal in the sensitivity list being the clock (except for an asynchronous set or reset if you really want/need this). Also take my advise and stick to using one clock per process it keeps the code more understandable and...- jeandelfrigo
- Post #2
- Forum: VHDL
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VHDL bidirectional port questions
John5788, This is a funny experiment, at least I hope it is because I cannot see the use of this code. For one thing I think this will give you timing issues when you want to implement this in real. Certainly at higher frequencies. What I think is the problem is that you have the four flip...- jeandelfrigo
- Post #2
- Forum: VHDL
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Using float signal in VHDL
dsimon19, VHDL and floats. A couple of questions you need to ask yourself first: synthesis or simulation? Do I really need floating pointor can I live with fixed point? Some explanation: VHDL supports floats for none synthesis. When you want to synthesize the trouble starts. Writing c <=...- jeandelfrigo
- Post #2
- Forum: VHDL
