I'm not sure if this would be possible to code in VHDL, but I would like to implement a two-way buffer using a CPLD (Complex Programmable Logic Device) where the input signal OE (OutputEnable) would determine the direction of the output.
So would it be possible to have two std_logic_vector's, say A and B, have their input and output determined based on a std_logic input signal OE?
So for example, if OE was high, then A would be the input, and B would be the output. Then if OE was low, then A would be the output, and B would be the input.
I can get this to work in ABEL HDL with INOUT signals but I can't seem to wrap my mind around how to approach this correctly in VHDL.
Thanks!
So would it be possible to have two std_logic_vector's, say A and B, have their input and output determined based on a std_logic input signal OE?
So for example, if OE was high, then A would be the input, and B would be the output. Then if OE was low, then A would be the output, and B would be the input.
I can get this to work in ABEL HDL with INOUT signals but I can't seem to wrap my mind around how to approach this correctly in VHDL.
Thanks!