variable used in for loop

[jrw0267]

i am writing a for loop for a shift opperation. The opperation should shift a bit vector to the right V number of positions. The easiest way to shift that I know of(new to VHDL so may be missing some easier way) is to use a loop and shift each position once over whcih is done V times. whenever trying to write a for loop with a variable left bound I recieve an error telling me the left bound must be a constant....any suggestions? code snippet follows

entity RT1 is
port(a:in bit_vector(3 downto 0); v:in integer;out bit_vector(3 downto 0));
end;

architecture shift1 of RT1 is
signal temp:bit_vector(3 downto 0);
shared variable count:integer:=v;
begin
temp(0)<=a(0);
temp(1)<=a(1);
temp(2)<=a(2);
temp(3)<=a(3);

process (temp)


begin
loopy: for i in count downto 0
loop
temp(0)<=temp(1);
temp(1)<=temp(2);
temp(2)<=temp(3);
temp(3)<='0';
end loop;
end process;
end shift1;


i know there may be other errors but im simply worried about making it work for now before worrying about the details

 

[heeckhau]

You could try to use sll (shift left logical), but I am not sure all tools can synthesize this.

You can also use shift_left from ieee.numeric_std, but then you will have to convert your bit_vector to unsigned first.

 

[jeandelfrigo]

Hello,

One general remark on loops in VHDL.

VHDL is a hardware description language.
It reacts different from software programming languages that tell processors what to do.

Even a mighty intel processor can only do one thing at a time (yes there are "behind the comma" discussion possible that can take several hours, preferably with sufficient beer or wine).

When you use a loop construction in software it means the processor will repeat a given set of instructions several times, depending on the loop condition.

When using VHDL, especially for code that needs to get synthesized loops and specifically for loops will or can lead to logic duplication.
There is no more efficient way to fill up an FPGA or other PLD that a few uncarefully used loops.

I just wanted to say this because it can be important for synthesis. When writing testbenches there is no real problem.

A good practice when using loops in synthesis code is to keep an eye on the output of your tool and the logic utilization. This is certainly so when you don't have much experience with either VHDL or a specific tool.

Regards,

jeandelfrigo