Hi all,
Following is the sample code for 26MHz generation from a 100MHz input clock.
entity c1hz is
port( clk:in bit; clkoutut bit);
end c1hz;
architecture behavior of c1hz is
begin
process(clk)
variable cnt : integer range 0 to 383;
begin
if(clk'event and clk='1') then
if(cnt=383)then
cnt:=0;
clkout<='1';
else
cnt := cnt+1;
clkout<='0';
end if;
end if;
end process;
end behavior;
Can somebody please tell me if this is right or not.
Following is the sample code for 26MHz generation from a 100MHz input clock.
entity c1hz is
port( clk:in bit; clkoutut bit);
end c1hz;
architecture behavior of c1hz is
begin
process(clk)
variable cnt : integer range 0 to 383;
begin
if(clk'event and clk='1') then
if(cnt=383)then
cnt:=0;
clkout<='1';
else
cnt := cnt+1;
clkout<='0';
end if;
end if;
end process;
end behavior;
Can somebody please tell me if this is right or not.