Hi guys
i wrote this code for a simple counter , 1 to 9. Apparently, it compiles properly including pin assignments but when i go to program, nothing show up on there. Ive tried other vhdl projects and they program fine. any ideas?
thanks!
code---------
Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY counter IS
PORT (CLOCK : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
End counter;
ARCHITECTURE mylogic OF counter IS
signal count : std_logic_vector (25 DOWNTO 0);
signal a : std_logic;
signal D : std_logic_vector (3 DOWNTO 0);
BEGIN PROCESS (CLOCK)
BEGIN
IF (CLOCK'EVENT AND CLOCK = '1') THEN
count <= count + 1;
END IF;
IF count = "01011111010111100001000000" THEN
a<='0';
END IF;
IF count = "101111101011110000100000000" THEN
a<='1';
count<="00000000000000000000000000";
END IF;
IF (a'EVENT AND a = '1') THEN
D <= D + 1;
IF D = "1001" THEN
D<="0000";
END IF;
END IF;
S(0) <= not ((not D(2) and not D(0)) or (D(2) and D(0)) or D(3) or D(1));
S(1) <= not ((not D(0) and not D(1)) or (D(1) and D(0)) or (not D(2)));
S(2) <= not ((not D(1)) or D(0) or D(2)) ;
S(3) <= not ((not D(2) and not D(0)) or (D(2) and D(0) and not D(1)) or (not D(2) and D(1)) or (D(1) and not D(0)));
S(4) <= not ((not D(2) and not D(0)) or (not D(0) and D(1)));
S(5) <= not ((not D(1) and not D(0)) or (D(2) and not D(0)) or D(3) or (not D(1) and D(2)));
S(6) <= not ((not D(1) and D(2)) or D(3) or (D(1) and not D(2)) or (D(2) and not D(0)));
END PROCESS;
END mylogic;
i wrote this code for a simple counter , 1 to 9. Apparently, it compiles properly including pin assignments but when i go to program, nothing show up on there. Ive tried other vhdl projects and they program fine. any ideas?
thanks!
code---------
Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY counter IS
PORT (CLOCK : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
End counter;
ARCHITECTURE mylogic OF counter IS
signal count : std_logic_vector (25 DOWNTO 0);
signal a : std_logic;
signal D : std_logic_vector (3 DOWNTO 0);
BEGIN PROCESS (CLOCK)
BEGIN
IF (CLOCK'EVENT AND CLOCK = '1') THEN
count <= count + 1;
END IF;
IF count = "01011111010111100001000000" THEN
a<='0';
END IF;
IF count = "101111101011110000100000000" THEN
a<='1';
count<="00000000000000000000000000";
END IF;
IF (a'EVENT AND a = '1') THEN
D <= D + 1;
IF D = "1001" THEN
D<="0000";
END IF;
END IF;
S(0) <= not ((not D(2) and not D(0)) or (D(2) and D(0)) or D(3) or D(1));
S(1) <= not ((not D(0) and not D(1)) or (D(1) and D(0)) or (not D(2)));
S(2) <= not ((not D(1)) or D(0) or D(2)) ;
S(3) <= not ((not D(2) and not D(0)) or (D(2) and D(0) and not D(1)) or (not D(2) and D(1)) or (D(1) and not D(0)));
S(4) <= not ((not D(2) and not D(0)) or (not D(0) and D(1)));
S(5) <= not ((not D(1) and not D(0)) or (D(2) and not D(0)) or D(3) or (not D(1) and D(2)));
S(6) <= not ((not D(1) and D(2)) or D(3) or (D(1) and not D(2)) or (D(2) and not D(0)));
END PROCESS;
END mylogic;