That code should work .. its the same when you code a multipiler on a uP ( so they theached us at University).
I think there should be some other thechnics too (something with cycle shift), but this is the easyest one.
Regards, Kriki
The problem is that you don't know what what number a group of bits represent.
i.E. 1111
-> unsigned = 15
-> signed = -7
and the same problem has the compiler ... why should he know what number it is, when you don't say that it's signed or unsigned.
The problem with the resulting sign could...
I try to program a counter who counts the clock'edges between the signal changes. The problem is that when the the next change occours, the counter doesn't reset back to 0.
Can anyone help me with that ??
process(lastdata, data, cclk, test, change, clk, i, rs)
begin
change <= data xor...
I think, the signed is only for real/integer types.
The STD_LOGIC is only the value of the voltage ( 0 or 1) and does not contain any numbers.
What i want to say is that there is no 2's compliment for a signal level (or a group of them).
Try to use integer/real instead of the STD_LOGIC_VECTOR...
Can anybody help me with shared variables ???
I want to use a counter in a subcomponent ,originally defined in the main component.
What way would be the best ???
Regards, Kriki
Take a look at http://www.jpeg.org
I think the spec sheet you'll get here:
http://www.iso.ch/iso/en/ittf/PubliclyAvailableStandards/c033876_ISO_IEC_15444-4_2002(E).zip
Regards, Kriki
How do you mean "how can i find the RAM module" ?
How to get to the downloadable files or what ?
If yes --> look for the CVS: browse
or take this one:
http://www.opencores.org/cvsweb.shtml/memory_cores/
Regards, Kriki
Cyclone is 256 pins max. only ... Look in Assignments->Device->Family-> PinCounts over 274
Could be Stratix II/Flex10k ...
Do you really need 8x 30Bit Input ??
Regards, Kriki
I tryed to make a program, that detects a signal and clocks it for the rest of the schematic.
So i wanted to ask, if this is a usefull programm or not or what could be done better.
The signal is rectangular and the Master Clock is 4 times of the data signal.
CODE:
LIBRARY ieee;
USE...
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