HELP: Can't get FIFO to work...

[pertierr]

Hello,

I am working on a Digilent D2SB board which has a Spartan 2E(300) on it with a 50Mhz oscillator, using Xilinx WebPack 6.2i. I am using two modules provided by xilinx in xapps, the basic 2X DLL(dll_2x.vhd) and the independent clock fifo from xapp131.

All i want to do, is write to the fifo at 100Mhz and read at 50Mhz. If both clocks are the same, it seems to work fine, but whenever I attempt to write at 100Mhz(2x clock) and read at 50Mhz(1x clock), i get more bytes of a specific value that I put in. For example, I wrote 100,000 bytes of the same value, but I get something like 130,000 out.

I have included my top-level code in this message.

I've been trying to get this to work for weeks now, if anyone know what i'm doing wrong i'll be forever grateful!!!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD;

library UNISIM;
use UNISIM.VComponents.all;

entity top_level is
Port ( clk : in std_logic;
led : out std_logic;
dout : out std_logic);
end top_level;

architecture Behavioral of top_level is
component dll_standard
port(CLKIN : in std_logic;
RESET : in std_logic;
CLK0 : out std_logic;
CLK2X : out std_logic;
LOCKED : out std_logic);
end component;
component fifoctlr_ic
port (read_clock_in: IN std_logic;
write_clock_in: IN std_logic;
read_enable_in: IN std_logic;
write_enable_in: IN std_logic;
fifo_gsr_in: IN std_logic;
write_data_in: IN std_logic_vector(7 downto 0);
read_data_out: OUT std_logic_vector(7 downto 0);
full_out: OUT std_logic;
empty_out: OUT std_logic;
fifostatus_out: OUT std_logic_vector(3 downto 0));
end component;
constant PIXELS_PER_FRAME : natural := 383624;
signal clk_1x : std_logic;
signal clk_2x : std_logic;
signal dll_locked : std_logic;
signal clkreset : std_logic;
signal mem_cycle : integer range 0 to PIXELS_PER_FRAME := 0;
signal mem_cycle2 : integer range 0 to PIXELS_PER_FRAME := 0;
signal color_count : integer range 0 to PIXELS_PER_FRAME := 0;
signal data_valid : std_logic;
signal fifo2_di : std_logic_vector(7 downto 0);
signal fifo2_do : std_logic_vector(7 downto 0);
signal fifo2_empty : std_logic;
signal fifo2_full : std_logic;
signal fifo2_put : std_logic;
signal fifo2_get : std_logic;
signal fifo2_gsr : std_logic := '1';
signal fifo2_status : std_logic_vector(3 downto 0);
signal led_signal : std_logic := '0';
begin
led<=led_signal;
clkreset<='0';
dll:dll_standard
PORT MAP( CLKIN=>clk,
RESET=>clkreset,
CLK0=>clk_1x,
CLK2X=>clk_2x,
LOCKED=>dll_locked);
--VGA FIFO: Pixels waiting to be put on VGA signal
fifo2:fifoctlr_ic
port map(read_clock_in=>clk_1x, --Should match reading process
write_clock_in=>clk_2x, --Should match writing process
read_enable_in=>fifo2_get,
write_enable_in=>fifo2_put,
fifo_gsr_in=>fifo2_gsr,
write_data_in=>fifo2_di,
read_data_out=>fifo2_do,
full_out=>fifo2_full,
empty_out=>fifo2_empty,
fifostatus_out=>fifo2_status);

--Writes to fifo. One frame is 383624 8-bit values.
--This process writes to fifo whenever it is not full.
process(clk_2x)
begin
if rising_edge(clk_2x) then
fifo2_gsr<='0';
fifo2_put<='0';
if fifo2_full='0' then
if mem_cycle<100000 then
fifo2_di<="00000011";
else
fifo2_di<="10101010";
end if;
fifo2_put<='1';
if mem_cycle/=(PIXELS_PER_FRAME-1) then
mem_cycle<=mem_cycle+1;
else
mem_cycle<=0;
end if;
end if;
end if;
end process;
dout<=fifo2_full;
--This process reads from FIFO.
--It counts to verify the number "00000011" has been read 100000 times in a frame.
process(clk_1x)
begin
if rising_edge(clk_1x) then
fifo2_get<=NOT fifo2_empty;
data_valid<=fifo2_get;

if data_valid='1' then
if color_count>100000 then
led_signal<='1'; --If this LED lights, something went wrong.
end if;
if mem_cycle2/=(PIXELS_PER_FRAME-1) then
if fifo2_do="00000011" then
color_count<=color_count+1;
end if;
mem_cycle2<=mem_cycle2+1;
else
mem_cycle2<=0;
color_count<=0;
end if;
end if;
end if;
end process;
end Behavioral;

 

[Kriki]

What size has the FIFO ???
And where is fifo2_status checked ??

Regards, Kriki

 

[pertierr]

The fifo is 512 bytes in depth, the entire FIFO code and documentation can be obtained at the Xilinx website under xapp131.

fifo2_status is a vector which states how full the fifo is. I am not using it because I am just checking the fifo2_full flag. Since I am generating the test data, if the fifo is full, the write process holds the next byte in the test pattern until the FIFO is not full and then continues writing.

I have tried everything, timing constraints, modyfing the structure of my code, using inferred counters, nothing fixes the problem.

I even tried using a 50Mhz write clock and a 25Mhz read clock, which should be well within the Spartan 2E capabilities, and i get the EXACT same problem. I put 100,000 bytes in, but i endup reading over 130,000 bytes out of that value.

Juan