Hello, I begin in VHDL and I try to create a demultiplexor 1 to 8 with a 30bits bus. If someone can help me!
this is the code: what must I do?
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity demux is
Port(
Signal sel: in std_logic_vector(2 downto 0);
Signal en: in std_logic;
Signal data0x: out std_logic_vector(29 downto 0);
Signal data1x: out std_logic_vector(29 downto 0);
Signal data2x: out std_logic_vector(29 downto 0);
Signal data3x: out std_logic_vector(29 downto 0);
Signal data4x: out std_logic_vector(29 downto 0);
Signal data5x: out std_logic_vector(29 downto 0);
Signal data6x: out std_logic_vector(29 downto 0);
Signal data7x: out std_logic_vector(29 downto 0);
Signal entree: in std_logic_vector(29 downto 0));
end demux;
architecture behavior of demux is
begin
process(sel,en)
begin
data0x<=(others=> '0');
data1x<=(others=> '0');
data2x<=(others=> '0');
data3x<=(others=> '0');
data4x<=(others=> '0');
data5x<=(others=> '0');
data6x<=(others=> '0');
data7x<=(others=> '0');
if(en='1')then
case sel is
when "000"=>data0x<=entree;
when "001"=>data1x<=entree;
when "010"=>data2x<=entree;
when "011"=>data3x<=entree;
when "100"=>data4x<=entree;
when "101"=>data5x<=entree;
when "110"=>data6x<=entree;
when "111"=>data7x<=entree;
end case;
end if;
end process;
end behavior;
this is the code: what must I do?
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity demux is
Port(
Signal sel: in std_logic_vector(2 downto 0);
Signal en: in std_logic;
Signal data0x: out std_logic_vector(29 downto 0);
Signal data1x: out std_logic_vector(29 downto 0);
Signal data2x: out std_logic_vector(29 downto 0);
Signal data3x: out std_logic_vector(29 downto 0);
Signal data4x: out std_logic_vector(29 downto 0);
Signal data5x: out std_logic_vector(29 downto 0);
Signal data6x: out std_logic_vector(29 downto 0);
Signal data7x: out std_logic_vector(29 downto 0);
Signal entree: in std_logic_vector(29 downto 0));
end demux;
architecture behavior of demux is
begin
process(sel,en)
begin
data0x<=(others=> '0');
data1x<=(others=> '0');
data2x<=(others=> '0');
data3x<=(others=> '0');
data4x<=(others=> '0');
data5x<=(others=> '0');
data6x<=(others=> '0');
data7x<=(others=> '0');
if(en='1')then
case sel is
when "000"=>data0x<=entree;
when "001"=>data1x<=entree;
when "010"=>data2x<=entree;
when "011"=>data3x<=entree;
when "100"=>data4x<=entree;
when "101"=>data5x<=entree;
when "110"=>data6x<=entree;
when "111"=>data7x<=entree;
end case;
end if;
end process;
end behavior;