Tek-Tips is the largest IT community on the Internet today!

Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!

  • Congratulations Mike Lewis on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!

confused with types 1

Status
Not open for further replies.

kofeyok

Programmer
Sep 7, 2004
3
0
0
CA
Hi everyone,
I am fairly new to VHDL and had several questions about types conversions that I've numbered for easiness of separating them. Any help would be greatly appreciated.

I am using signed type throughout my program. Now, there is one third party function that outputs std_logic_vector, that I have to use. The function looks like its std_logic_vector signal is in signed format (the sine wave with positive and negative values). 1. Can I just assume that it's in 2's compliment format similar to signed? In other words, how does STD_LOGIC_VECTOR holds signed numbers?

2. I understand that if I would like to match it to my internal signals, I would have to cast that signal to SIGNED. So, can I do SIGNED(STD_LOGIC_VECTOR signal) to do that? What would be the result of the above statement? Would it take the signal inside and convert it to 2's comliment? That would be useless for me if the signal is already in 2's compliment. If that's not correct, please let me know how can go around this.

3. I suppose STD_LOGIC_VECTOR can hold any format (1's, 2's or just magnitude) as long as you keep in mind in which context you are using it. However, the moment you start using SIGNED function, how does VHDL compiler recognize the numbers from then? Does it still treat them as STD_LOGIC_VECTOR and 'makes a note' for itself that it contains 2's compliement?

4. I've read that ieee.std_logic_arith and ieee.numeric_std are mutually exclusive libraries that you cannot use at the same time. Maybe using one or another one would somehow answer my questions above..

Big thanks in advance!
Kofeyok


 
I think, the signed is only for real/integer types.

The STD_LOGIC is only the value of the voltage ( 0 or 1) and does not contain any numbers.

What i want to say is that there is no 2's compliment for a signal level (or a group of them).

Try to use integer/real instead of the STD_LOGIC_VECTOR or convert the signal on your own like

signed_STD_LOGIC_VECTOR = not unsigned_STD_LOGIC_VECTOR + 1

or try to use an extra bit for the sign.

i.E. you have the sin in 8bit-format, you use a 9-bit format with the 9th. bit as sign-bit.
You can do that like this:

if(sin = "00000000") then
sign <= not sign;
end if;

I hope that is what you ment and i could help you.




Regards, Kriki
 
Thanks for the answer Kriki,
I think your approach will work. The only thing to figure out now is the multiplication I have to do with 'signed' numbers. I guess an IF statement which checks whether one or both numbers are negative should be introduced to decide whether the answer is negative.

I've tried another approach though. I saw example of the code where it takes integer, use to_signed() function and then apply std_logic_vector() on the result to get 2's compliment. I don't know how that works, because I was thinking before that SIGNED type is the same as std_logic_vector type, but when you are using SIGNED, the compiler considers the signal to be STD_LOGIC_VECTOR in 2's compliment. Also, I thought that the multiplication function "*" needs to know if it's 2's compl. or just a magnitude. Maybe it is - that's where I am still confused.

Here is the code that worked for me. I needed to multiply two numbers making sure that the compiler knows that they are in 2's compliment. So, I casted it to 'signed', multiplied and then casted back to 'std_logic_vector':
Code:
signal sigDATA_IN2_OVERSAMPLED: std_logic_vector (.. downto 0);
signal sigGENERATED_WAVE: std_logic_vector (.. downto 0);
..
..
sigDATA_SIGNED <= signed(sigDATA_IN2_OVERSAMPLED);
sigCARRIER_SIGNED <= signed(sigGENERATED_WAVE);
prtDATA_OUT <= std_logic_vector("*"(sigDATA_SIGNED, sigCARRIER_SIGNED));

Hey, does it mean that signed() is just the statement like in C, that tells that the STD_LOGIC_VECTOR in parenthesis is in 2's compliment representation? and in fact, there is no actual SIGNED type - it's just a way to show the compiler whether it should use 2's compliment operations or the regular ones?


THANKS!
 
The problem is that you don't know what what number a group of bits represent.

i.E. 1111
-> unsigned = 15
-> signed = -7

and the same problem has the compiler ... why should he know what number it is, when you don't say that it's signed or unsigned.

The problem with the resulting sign could be done easily with an xor.

Arithmetical Sign-Bits with XOR

N1 N2 Result A B Q
pos * pos -> pos 0 0 0
neg * pos -> neg 0 1 1
pos * neg -> neg 1 0 1
neg * neg -> pos 1 1 0


Hope it's working fine.

Regards, Kriki

Regards, Kriki
 
Using XOR gate would help to decide on the sign of the operators. Then, depending on the sign, I would have to cast it properly or just translate negative numbers into positive by flipping the bits and adding one. After that, do multiplication of positive #s and change the result into 2's compliement if required. Is that what you've ment?

Does my code above using 'casting' make sence though if I am sure that two numbers are in 2's compliment?

Thanks



 
That code should work .. its the same when you code a multipiler on a uP ( so they theached us at University).

I think there should be some other thechnics too (something with cycle shift), but this is the easyest one.


Regards, Kriki
 
Status
Not open for further replies.

Part and Inventory Search

Sponsor

Back
Top