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Quartus will not dedicate a location for that constant. It will work the same way that your C compiler works. It will shrink things even further that that even, say if you had a constant and were OR'ing it with another bit, it would detect the instance where the constant bit is 1 and would...

I usually do that kind of thing with a shift register. Of course it depends on all kinds of things, like how often the button is to be pressed, and what kind of debounce you might need. For a physical button you probably need a very large debounce of say 250ms or more, unless that is built in...

Sorry for the long delay in writing. First you are going to have to find out how to create those effects algorithmically (ie regardless of the implementation - in this case gates in an FPGA). From there we will have to come up with a way of implementing in an FPGA. I guess there are some...

Usually there is a pragma that you set in your VHDL, or maybe a setting in your synthesis tool to say "preserve heirarchy". I think that is what you use to keep the signal names preserved also. I forget exactly what it is, but in any event its usually different depending on your synthesis tool...

Nice code. Well laid out, nice comments. Nothing seems obviously wrong. what is happening with your ram read? The most likely problem is that your counts and reads etc don't line up. If you are new at this its often easy to screw up the functional timing because you forget about the clock...

go to altera's website. they have documents on how to use core's. http://www.altera.com/products/ip/dsp/transforms/m-ham-fft.html thats the location of the latest version (2.1.0) and there is a button there to "view literature". Maybe if you search their knowledge base you might find some...

just a note. I am guessing that it will be really hard to implement in hardware unless you have a DSP embedded in your device. A quick google search finds this paper: http://venus.elfak.ni.ac.yu/IMPEG/DigitalSystem.pdf which looks like it could be implemented, but its going to take a lot of...

ieee.math_real package has a function sqrt. It may only be behavioural, if it is and you need a working function that you can synthesize, you will probably have the most luck looking for a function from your vendor (fpga, asic, whatever) -- http://www.lateralsands.com/

one way to do that is keep a copy of start on the last clock and check to see if the last value was 0 and the current is 1... therefore its a rising edge. old_start <= start; -- rising edge check if (start = '1' and old_start = '0') then blah; end if; unless of course you wanted the whole...

oops 2 should read. 2. any signal must only be driven from one process -- http://www.lateralsands.com/

amitsdsu Sure you can do that if you want. However in order to do so you must create multiple processes. One for you falling edge signal and another for your rising edge signal. Then a final process, or just some logic to create your resulting signal. You must stick to these...

I assume you generated this code with some kind of vendor tool. Really you could do it either way, but to avoid mistakes I would regen (thats probably the only pro/con of doing it either way) -- http://www.lateralsands.com/

what you are probably looking for is generate. my_gen_choice : if ch = choice generate begin your_signals <= some_value; end generate my_gen_choice; my_gen_choice1 : if ch = choice1 generate begin your_signals <= some_other_value; end generate my_gen_choice1; it can be used in various...

There is an ieee math_real package that seems to have COS/SIN functions. I have never used it, but Im sure it works ok. Not sure if its synthesizable or behavioural only. -- http://www.lateralsands.com/

why didn't your xilinx ram work? exactly what did it do (and not do)? -- http://www.lateralsands.com/

start by writing what needs to be done in a kind of psuedo code algorithm style. if you want to post that I can kick you in the right direction maybe. obviously you will be starting with a ADC (and I guess ending with a DAC), both outside of the FPGA (unless you have an FPGA with that...

the std library textio package has the functions you want. read and readline, write and writeline are the main functions for reading and writing. readline and writeline read and write a line of data from/to the file, you then use read and write to extract structures of data from the file. You...

thats going to chew up the memory and speed of your simulation. but its sometimes nice to have all the ram available like that. One thing you could do is convert to an integer when storing the data (and on read convert back). that will speed it up a little. Look up the ram thats on the...

there is probably some state machine that gets reset. don't know why it would cause a problem, although 1 clock is kind of short, I would generally reset for a little longer in case there is some buffering of the reset signal. The only thing I can suggest is going through xilinx datasheets and...

the pragma's are used by various synthesizers to tell it different things (ie translate_off = ignore this code till you see translate_on) for some reason I have this feeling that many DLL's don't really simulate, you have to do it on the real device to see what the output will be. But it seems...