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About how Max Plus/Quartus handles "constant" types.

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nic33

Programmer
Jul 9, 2004
5
US
I'm wanting to know more about how constants are used in VHDL.

First of all, I know you can only declare a constant within the architecture decloration like:

ARCHITECTURE Behavior OF unit IS
CONSTANT n : INTEGER := 10;
CONSTANT x : STD_ULOGIC_VECTOR(3 DOWNTO 0) := 12;
---so on----

I'm curious on what happens with a constant decloration when it actually gets burned on a chip. The fact that you must declare the type as an integer or a vector makes alarm bells in my head go off. Having to do this decloration makes me think that when I burn my device a segment of it is dedicated to holding the value of the constant, and then everything that refers to the constant just links to that place burned on my device. This is not what I want. I want constants in the sense of C Programming, where the compiler replaces all instances of a constant in my code with the value I have given that constant at compile time.
Meaning:

CONSTANT n : INTEGER := 10;
...snip...
MyOUTPUT <= n;

shouldn't take anymore hardware then just:
MyOUTPUT <= 10;

I'm also wanting to use constants in my entity decloration block, because I'm needing to define different input and output vector lengths based on some constants.

Clarity would give me some peace of mind.
Thanks for your input!
-Nic
 
Quartus will not dedicate a location for that constant. It will work the same way that your C compiler works.

It will shrink things even further that that even, say if you had a constant and were OR'ing it with another bit, it would detect the instance where the constant bit is 1 and would shift the '1' further down the chain (since the result will always be 1). Or if the constant were 0 then it would remove the OR and simply replace it with a wire.

--
 
Cool! I was hoping so, but the syntax made it seem funny. VHDL seems to be so data-type sensitive, even when the two datatypes seem absolutely compatible. Like an unsigned vector of 4 bits should hold any integer value 0 to 15.
But when you assign them you have to run "conv_integer" or "conv_unsigned", which still makes it convienient.

In anycase our design is almost finished, and simulations are going well.

Thanks for your reply!
-nic
 
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