Case Statement Construction 1

[daklub]

Hello,

I have a case statement that uses expressions derived from a generic input to the module and while it compiles and simulates, ISE does not like it much [and it doesn't agree with strict VHDL coding either] and I am looking for a better way to construct it. Here's a sample of what I'm trying to do:

entity Recodrd is
generic( choices : integer)
port(ch : in integer rantge 0 to 2047;
....
);
...

constant choice1 : integer := 0
constant choice2 : integer := choices
constant choice3 : intenger := choices*2;

....

case ch is

when choice =>
when choice1 =>
when choice2 =>

end case;

choice works fine, but choice1 and choice2 give warnings as not being 'locally static' How can I make then locally static, but still retain the power of the generic? (I need the module to scale from choices = 1 to 768)

 

[VHDLguy]

what you are probably looking for is generate.

my_gen_choice : if ch = choice generate
begin
your_signals <= some_value;
end generate my_gen_choice;

my_gen_choice1 : if ch = choice1 generate
begin
your_signals <= some_other_value;
end generate my_gen_choice1;

it can be used in various different ways and the logic is only generated when the statement is true. usualy good for generics, but I guess it depends on what you intend to do.

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