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Your code is correct if it is placed in a synchronous (clocked) process. Implementing this combinatorially is certainly not recommended. Theoretically it should work, but in practice you have no control over the combinatorial delay of the different signals which may lead to rubbish. Also if the...

Each "if" should be followed by a "end if" Now, two constructions are valid: 1) if MemWrite='1'then data_mem(addr):= write_data; else if MemRead='1' then read_data <= data_mem(addr) after 10ns; end if; end if; 2) (Notice the "elsif" in one word) if MemWrite='1'then...

try this: process(inports,id_in_sig) begin for N in inports'range loop if id_in_sig = conv_std_logic_vector(N, id_in_sig'length) then time_out <= inports(N); end if; end loop; end process;

First of all, it's not a good idea to use a variable here. Add a signal declaration in your architecture (before "begin") signal cnt: integer range 0 to 4 :=0; Secondly, Instead of cnt := cnt+1, try: if cnt=4 then cnt <= 0; else cnt <= cnt+1; end if; If this doesn't solve to...

You got a bit confused. An architecture is a certain implementation of an entity. When you simulate or implement this only one of the architectures will be used. solution: ARCHITECTURE beh OF mux4 IS signal ftemp: std_logic; BEGIN WITH s SELECT ftemp <= D(0) WHEN "00", D(1)...

if sig1 and sig2 are std_logic_vectors, I would just make a sig3 which is the concatenation: sig3 <= sig1 & sig2; Then just WAIT ON sig3;

Try this: process variable cntvar: natural; begin cntvar := cnt; for i 0 to 2 loop cntvar := cntvar + 1; end loop; cnt <= cntvar; end process;

The process in the videoOutClockImpl architecture is a synchronous process, but you forgot to write "if (rising_edge(clk))" A synchronous process should always look like this: process(CLOCK11) begin if (rising_edge(CLOCK11)) then ... end if; end process; If it was the intention to...