clk divider not working as expected 1

[andychess86]

thread284-1502031

Hi, using the advice given by the user of the alias: jeandelfrigo, I wrote code to divide a 125 MHz clock into a 5 MHz. I use a counter that counts from 0 to 4 and when the counter is equal to 0,1, or 2 I let the clk be a '1'. otherwise I let clk be a '0'. However when I look at signal on chipscope (using the 125 MHz signal as the clock in chipscope), I get a signal that is high for 3 (which I expected) and low for 4( I would expect it to be low for 2)

here is the essence of my code:
process(clkin)
variable cnt : integer range 0 to 2 :=0;
begin
if (clkin'event and clkin='1') then
if (cnt=0 or cnt=1 or cnt=2) then
clktemp <= '1';
else
clktemp <= '0';
end if;
cnt := cnt+1;
end if;
end process;

Anyone know whats going on? Thanks, Andy

process

 

[andychess86]

i was playing around with the my code above but originally the line that reads:

variable cnt: integer range 0 to 2 :=0;

initially read :
variable cnt: integer range 0 to 4 :=0;

sorry for the confusion

 

[Robbe147]

First of all, it's not a good idea to use a variable here.
Add a signal declaration in your architecture (before "begin")
signal cnt: integer range 0 to 4 :=0;

Secondly, Instead of cnt := cnt+1, try:

if cnt=4 then
cnt <= 0;
else
cnt <= cnt+1;
end if;

If this doesn't solve to problem, observe cnt in chipscope as well.


Are you implementing this in a Xilinx fpga? If you are using clktemp as a clock lateron in your design, I must agree to jeandelfrigo to take a look at DCM's.