4:1 MUX issue

[stryker213]

Hello, I'm having some trouble implementing my 4:1 MUX and was hoping I could get some input. My main issue is this, the MUX will need to have an output of 'Z' when EN=0. I coded the following:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux4 IS
Port(D: in std_logic_vector(3 downto 0);
s: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
EN: in std_logic; f: OUT STD_LOGIC);
END mux4 ;

ARCHITECTURE beh1 OF mux4 IS
BEGIN
WITH s SELECT
f <= D(0) WHEN "00",
D(1) WHEN "01",
D(2) WHEN "10",
D(3) WHEN OTHERS;
END beh1;

ARCHITECTURE beh2 OF mux4 IS
begin
with EN select
f<='Z' when '0',
null when others;
end beh2;

I just can't figure out how to fix my error!

 

[Robbe147]

You got a bit confused. An architecture is a certain implementation of an entity. When you simulate or implement this only one of the architectures will be used.

solution:

ARCHITECTURE beh OF mux4 IS
signal ftemp: std_logic;
BEGIN
WITH s SELECT
ftemp <= D(0) WHEN "00",
D(1) WHEN "01",
D(2) WHEN "10",
D(3) WHEN OTHERS;

f <= ftemp when EN='0' else 'Z';

END beh;


--------------------------------------------
Another way to write this:

ARCHITECTURE beh OF mux4 IS
BEGIN
process(s,D,EN)
begin
if (EN='1') then
case D is
when "00" => f <= D(0);
when "01" => f <= D(1);
when "10" => f <= D(2);
when others => f <= D(3);
end case;
else
f <= 'Z';
end if;
end process;

END beh;