The possibility to use for-loop instead of a lot of whens?

[moberg2236]

To be able to make the design i'm working on mor general so it will be easier to change,change the number of inports for example.
Therefore i would like to replace the code below with a for loop.



time_out <= inports(0) when id_in_sig = "0000" else
inports(1) when id_in_sig = "0001" else
inports(2) when id_in_sig = "0010" else
inports(3) when id_in_sig = "0011" else
inports(4) when id_in_sig = "0100" else
inports(5) when id_in_sig = "0101" else
inports(7) when id_in_sig = "0111" else
inports(7) when id_in_sig = "0111" else
inports(8) when id_in_sig = "1000" else
inports(9) when id_in_sig = "1001" else
inports(10) when id_in_sig = "1010" else
inports(11) when id_in_sig = "1011" else
inports(12) when id_in_sig = "1100" else
inports(13) when id_in_sig = "1101" else
inports(14) when id_in_sig = "1110" else
inports(15) when id_in_sig = "1111";

With different variations, i have tested the following for loop


snurra: for N in 0 to interrupt_in_size generate
time_out<= inports(N) when id_in_sig = conv_std_logic_vector(N, id_size);

end generate;

The problem is now that i cant find a way to make it work in any way, as you see, the for loop will result in that time_out will get assigned multiple values, but i only want it to be set to one value when a certain id_in_sig is set,

For your information, inports is an array of size 16 of std_logic_vectors (15 downto 0)

Time out is a std_logic_vector(15 downto 0)
id_in_sig is a 4 bit id.

Making a for-loop works for me in every other case, except for this one where i want 1 signal to have 16 possible values depending on the id_sig

This is not a problem to make my code work, but since figuring this one out, probably could help speeding up my coding i would appreciate any help.

 

[Robbe147]

try this:

process(inports,id_in_sig)
begin
for N in inports'range loop
if id_in_sig = conv_std_logic_vector(N, id_in_sig'length) then
time_out <= inports(N);
end if;
end loop;
end process;