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wait for statement inside a process
Hi, You can't use the "wait for" in state machine design. For making delays, you can define the new states. The number of new states depend on your clock frequency. For example, if your frequency is 10ns , you need one new state for delay 10ns. -
What is wrong with my code?
Hi bluesource, Your code has got error because you used the variable "exp_diff" for the function SHR. It should be constant. -
Delay problem
Hi, I think this clause only work in functionnal simulation. The timing simulation will be done after the synthesis of your design but the synthesis don't support any assignment with "after ... -
help urgent!!! binary to bcd converter
Hi, You can see more informations in this link : http://www.tek-tips.com/viewthread.cfm?qid=840645 Or you can search in google with keyword "bcd to binary vhdl". There are many examples or source code for reference. Good luck. -
help urgent!!! binary to bcd converter
Hi, I think you have recently used the VHDL. Remember that VHDL is the language to design the hardware but not the software. Your program seems to be used for C language in computer. I think the trouble is here : FOR i IN 0 TO 9 loop IF D(10-i)='1' then r(5+i DOWNTO 0) :=... -
Duty Cycle Counter
The "while loop"in VHDL language can be used in behvioral simulation but can not be synthesis. So, don't use "while loop" for counter in VHDL. Try to solve your problem with the state machine. I can help you to do it but I don't know when the loop of the "lower" counter finish, the upper... -
state machine
Hi, I try to help you with my source code. I don't know how many beep 500ms you want ? But i think you can modify the source ode as you like. I suppose the clock frequency is 1MHz. Here is the state machine by using one process. I like to design this with 2 process but i think you are familar... -
state machine
Hi Brian, To beep sound with different speeds, you can define new state. I suppose "010". The idea is as follows : ............ variable count : integer range 0 to MAXTIME; --you can define MAXTIME as you like signal SPEED : integer range 0 to MAXTIME; --SPEED is the time you want to change... -
Signal xx cannot be synthesized, bad synchronous description
Hello, You cannot use the structure for the synthesis : If (clk'event and clk='1') ..... else ... end if. Try to design your ALU with If (clk'event and clk='1') ..... end if. If you cannot do, give me the description of ALU. I will help you. Normally, ALU is purely combinatoire. So... -
VHDL While Loop Problem
Try to change the value of iteration in statement "while ((not endfile(f_initfile) and (v_loop < X))) loop" . ChooseX=10000,9999. If it can be compiled, the compiler limit the loop variable. -
VHDL While Loop Problem
Hello, Try to correct the scope of variable variable v_loop : integer range 0 to 65535.
