Duty Cycle Counter

[jvet4]

Hi,

I am trying to develop code to calculate the Duty Cycle of a temperature sensor output (a square wave) and I wanted to see if anyone has developed a duty cycle counter?

My approach has been as follows:
1. initialze two counters to 0
2. look for a rising edge
3. Enter the "upper" count loop which I attempted to make a while loop (i.e. while signal = '1' count <= count +1)
4. Once the loop terminates (i.e. signal = '0') then the "lower" counter begins and counts "while signal = '0'

I am using Lattice ispLEVER and I keep getting an error that indicated that my loop is not terminating and I should set the attribute syn_looplimit, however this does not solve the problem.

Has anyone tried to develop this type of circuit or have any suggestions as to a better approach.

Thanks,
Jason

 

[bonami172]

The "while loop"in VHDL language can be used in behvioral simulation but can not be synthesis. So, don't use "while loop" for counter in VHDL.
Try to solve your problem with the state machine. I can help you to do it but I don't know when the loop of the "lower" counter finish, the upper counter continue to count ou no. .