VHDL While Loop Problem

[nyep]

I am currently trying to compile and simulate a vhdl ROM file. I am having problem with the while loop, which is used to read the ROM. The following is the vhdl-code:

entity mc8051_rom is

generic (c_init_file : string := "mc8051_rom.dua");

port (clk : in std_logic; -- clock signal
reset : in std_logic; -- reset signal
rom_data_o : out std_logic_vector(7 downto 0); -- data output
rom_adr_i : in std_logic_vector(15 downto 0)); -- adresses;

end mc8051_rom;

architecture sim of mc8051_rom is

type rom_type is array (65535 downto 0) of bit_vector(7 downto 0);
signal s_init : boolean := false;

begin

-----------------------------------------------------------
-- rom_read
------------------------------------------------------------

p_read : process (clk, reset, rom_adr_i)
variable v_loop : integer range 0 to 65536;
variable v_line : line;
variable v_rom_data : rom_type;
file f_initfile : text is in c_init_file;
begin
if (not s_init) then
v_loop := 0;
while ((not endfile(f_initfile) and (v_loop < 65536))) loop
readline(f_initfile,v_line);
read(v_line,v_rom_data(v_loop));
v_loop := v_loop + 1;
end loop;
s_init <= true;
end if;
if (clk'event and (clk = '1')) then -- rising clock edge
rom_data_o <= to_stdlogicvector(v_rom_data(conv_integer(unsigned (rom_adr_i))));
end if;
end process p_read;

end sim;

The error statement from Quartus II is :

"Error: VHDL Loop Statement error at mc8051_rom.vhd(103): loop must terminate at or before 10000 iterations"

Can anybody help me solve this problem?Thanx very much.

 

[bonami172]

Hello,
Try to correct the scope of variable variable v_loop : integer range 0 to 65535.

 

[nyep]

i've done that already, but i still got the same error statement and could not be able to compile.

 

[bonami172]

Try to change the value of iteration in statement "while ((not endfile(f_initfile) and (v_loop < X))) loop" . ChooseX=10000,9999. If it can be compiled, the compiler limit the loop variable.