Multiplication with shift and add

[ashfaq2419]

dear friends,

i am implementing a structure, in which i have to do some multiplications and additions/subtractions. for multiplication i am using shift-add technique e.g. if my input number is 'a' and it has to be multiplied by 51, i simply do it like (a<<5)+(a<<4)+(a<<1)+a. but the problem is with the sign. e.g. a=-32 and i am using 10 bits to represent it.

now the question is that i know that the multiplicand is always positive i.e. 51, but input number can either be positive or negative. how can i manage this thing so that the sign of the output is always correct. please guide me in detail and i have tried a lot to understand the phenomenon but to no avail.

regards

 

[flymolo]

Hi
Can you please provide some code? What is the width of a signal for the result.
I dont think you will get better result by coding it by hand. Synthesizers nowadays will infer constant coefficient multiplier efficiently. I would try this:

library ieee;
use ieee.numeric_std.all;
...
constant c : unsigned(5 downto 0) := to_unsigned(51, 6);
signal a : signed(9 downto 0);
signal y : signed(15 downto 0);
begin
y <= a*c;
...

 

[flymolo]

Sorry there's a mistake. The code should be:

library ieee;
use ieee.numeric_std.all;
...
constant c : signed(6 downto 0) := to_signed(51, 7);
signal a : signed(9 downto 0);
signal y : signed(16 downto 0);
begin
y <= a*c;
...

there's always a little confusion with signed/unsigned arithmetic Never mix signed/unsigned like i did
If you want to stick with your initial description im not sure for now. But like in my case maybe extending the constant with leading 0 will help. You would have 10bit and 7bit operands, result will be 17 bit wide.

 

[flymolo]

I checked implementation on Spartan3 FPGA, you will get 47 LUT's (4-input) with description above. Its pretty cheap