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conversions....
- Thread starter ladybug
- Start date
--doesn't deal with sign
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity conversion is
end conversion;
architecture test of conversion is
signal one : std_logic_vector(3 downto 0);
signal two : real;
signal three : integer;
begin
main : process
begin
two <= -10.1;
for i in 1 to 200 loop
wait for 100 ns;
two <= two + 0.1;
end loop;
wait;
end process;
three <= integer(two);
one <= conv_std_logic_vector(three,4);
end test;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity conversion is
end conversion;
architecture test of conversion is
signal one : std_logic_vector(3 downto 0);
signal two : real;
signal three : integer;
begin
main : process
begin
two <= -10.1;
for i in 1 to 200 loop
wait for 100 ns;
two <= two + 0.1;
end loop;
wait;
end process;
three <= integer(two);
one <= conv_std_logic_vector(three,4);
end test;
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