Simple Binary to BCD conversions

[Mynci]

hi, i know this is simple stuff, but it has been driving me mad trying to implement it. i have a number stored as a 32bit std_logic_vector. i need to convert it into bcd for display.
im sure this is fantastically simple and annoying to be asked how to do it, but im yet to find a simple (and non rescource hungry) method.

if anyone could point me at any guides to how this should be done i would very, very much appreciate it, i have read through just about all the information i can dig up on google and they all seem to implement the conversion in parallel (for a 32 bit numbers this seems unweildy) or in other ways that i simply cant get my head around.

i have made an attempt to implement the circuit discussed here:

http://www.eetkorea.com/ARTICLES/2000JUN/2000JUN27_PL_CT_AN6.PDF

As i can see if i chained them together it would provide me with a possible solution, unfortunatley my attempts at creating the circuit have been entirely unsuccessful (i can post the code, if it would be helpful).

any guidance on this would be very much apreciated.

cheers
mynci

 

[Mynci]

thank you so very much, thats got it a treat, there seemed to be a bit of an error in my last logic, i tried to boild down all the muxes and that into 'purer' logic, it didnt quite work though.

as folows is the final working code, just to get it on record, to help anyone lese trying to do this.

once again, i cant thank you enough for your help, i would have spent hours and hours longer trying to catch my errors, which are no doubt obvious to an old hand like yourself

thanks again
mynci

code(for one unit, string them together to do more than one digit):

-------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.calculator_package.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SerBCDBin is
Port ( MODin : in std_logic;
clk : in std_logic;
init : in std_logic;
rst : in std_logic;
MODout : out std_logic;
DigitOut : out key_type
);
end SerBCDBin;

architecture Behavioral of SerBCDBin is
signal Q : std_logic_vector(3 downto 0);
signal MODOut_int : std_logic;

begin

process (clk)

begin

if (clk'event) and clk = '1' then
if init = '1' then

if rst = '1' then
Q <= "0000";
else

if MODout_int = '1' then
Q(3) <= Q(3) and Q(0);
Q(2) <= Q(0) xnor Q(1);
Q(1) <= not Q(0);
Q(0) <= MODin;
else
Q(3 downto 1) <= Q(2 downto 0);
Q(0) <= MODin;

end if; --modtest for 5 or greater
end if;--init
end if; --rst
end if; --clk
end process;
----------------------------------------------------------------------------------------------------------------

process (Q)

begin
if Q >= "0101" then
MODOut_int <= '1';
else
MODOut_int <= '0';
end if;
end process;
----------------------------------------------------------------------------------------------------------------
MODOut <= MODOut_int;

----------------------------------------------------------------------------------------------------------------
process (Q)
begin
case Q is
when "0000" => DigitOut <= zero;
when "0001" => DigitOut <= one;
when "0010" => DigitOut <= two;
when "0011" => DigitOut <= three;
when "0100" => DigitOut <= four;
when "0101" => DigitOut <= five;
when "0110" => DigitOut <= six;
when "0111" => DigitOut <= seven;
when "1000" => DigitOut <= eight;
when "1001" => DigitOut <= nine;
when others => DigitOut <= no_key;
end case;
end process;

end Behavioral;