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std_logic_vector
If position 8 is the sign, and you want to shift right by two (i.e. divide by 4 and dropping the remainder), don't you mean: DOUT <= DIN(7) & "00" & DIN(6 downto 2); ?? -
std_logic_vector
My only comment is that it is that there is no question how the extended input will synthesize. The function (while nice and generic) is harder to follow for newbies. Keep in mind: generic code and functions are EXCELLENT coding technique. The only problem is when synthesis comes into... -
std_logic_vector
DOUT <= ('0' & DIN0) + ('0' & DIN1); Good luck! -- Brian -
Repetitive code (Newbie)
You can instantiate your component using a 'generate' statement: rom_generate: for i in 0 to 3 generate dummy: rom16x1 port map ( a3 => input(3), a2 => input(2), a1 => input(1), a0 => input(0), o => output(i) ); end... -
unable to generate a pulse on external pin event
You MUST have a periodic clock signal in order to check the external pin. It should also be a reasonable frequency. You are essentally sampling the input pin, and need to be able to detect a change on the external pin. If the clock were really slow (say 1 Hz) you could easily miss a button...
