std_logic_vector 2

[naraic]

Hi.

The line below is causing me problems.

DOUT <= DIN0 + DIN1;[\code]

DIN0 and DIN1 are inputs to the entity of type std_logic_vector(7 downto 0), and DOUT is an output of the entity of the type std_logic_vector(8 downto 0).

The problem is that the buses are of different width, and this causes an error. If both DIN0 and DIN1 are equal to &quot;11111111&quot;, I want DOUT to equal &quot;111111110&quot;. Is there any way I can do this without causing the error?

Thanks

 

[bfuchs]

DOUT <= ('0' & DIN0) + ('0' & DIN1);

Good luck!

-- Brian

 

[naraic]

Thanks. Also, are there any shift operations or functions , such as

srl, sra, sll etc[\code] that work on type std_logic_vector?

 

[bfuchs]

My only comment is that it is that there is no question how the extended input will synthesize.

The function (while nice and generic) is harder to follow for newbies.

Keep in mind: generic code and functions are EXCELLENT coding technique. The only problem is when synthesis comes into play... I have seen tools choke on some functions, and produce unexpected results.

If you are using a tried-and-tested function -- great. If you are trying a new one, build a chip using only one new function and verify it works.

Nothing is more difficult than debugging code you don't fully understand...

 

[naraic]

Ok. Say i don't want a general functions for right shifting. Say I know that

DIN[\code] needs to be shifted right by 2. Assuming [code]DIN[\code] and [code]DOUT[\code] are 8 bit wide std_logic_vector buses, and I want them to represent signed integers (e.g. they keep the sign when shifted), could I say

[code]  DOUT <= DIN(7) & DIN(7) & DIN(5 downto 0); [\code]

This removes the need for that function.

 

[bfuchs]

If position 8 is the sign, and you want to shift right by two (i.e. divide by 4 and dropping the remainder), don't you mean:

DOUT <= DIN(7) & &quot;00&quot; & DIN(6 downto 2); ??

 

[senjed]

The write code would be :
DOUT <= DIN(7) & DIN(7) & DIN(7) & DIN(6 downto 2)
This way you'll keep the sign.

 

[naraic]

It should be

DOUT <= DIN(7) & DIN(7) & DIN(7 downto 2);[\code]
This is essentially the same as yours, senjed. Thanks.

 

[bilba]

So does somebody have a more generic shift right operator for use with standard_logic_vector? I will be needing to shift right, but it will vary based on my data. I will be dynamically scaling, so I need a more generic approach. I have only spent a little bit of time on it so far, but thought that someone else must have approached this before. Thanks!

 

[naraic]

Yes.

library ieee;
use ieee.std_logic_signed.all;
.
.
signal a,b: std_logic_vector(10 downto 0);
.
.
a <= SHR(a,&quot;11&quot;); --shifts a 3 times right
.
.[\code]

SHL is a similar shift left.

Ciaran Hughes.