Xilinx Pipelined Divider Problem

[JTRAETS]

Hi,

I'm working with the xilinx divider core, it seems to be failing. When I reset the FPGA it sometimes (after about 300 resets) gives back wrong outputs. This will stay this way until it's reloaded.

Is anyone else having problems with this core?


Greetz
Johan

 

[VHDLguy]

what are the wrong outputs? it might give some clue.

How are you reseting the core?

I have never used the core, but its probably something general rather than related specifically to the core.

--

http://www.lateralsands.com/

 

[JTRAETS]

The core only holds 2 inputs, 1 output and a clock input.

The main problem is that it can't be resetted, so it's dividing al the time.

I'm sure it's not something general because it seems that I fixed it. I gated the clock input ( I know, not good design practise) so now it's only dividing when in a certain state (the program is controlled with a fsm).

I think that the problem is the fact that it is dividing all the time, and that after a reset something goes wrong. I used the core a couple of times already but never had this problem.

I want to thank you for your help

Greetz Johan

 

[VHDLguy]

huh?

When you say 2 inputs and 1 output, are you talking multibit inputs and outputs, or 2 bits in 1 bit out?

cause 2 bits in and 1 out doesn't really make much sense.
1 / 0 is invalid (maybe thats your reset problem regardless of how this thing works)
0/1 = 0
1/1 = 1
0/0 = ? 0 i guess, but maybe invalid?

anyway you get my point, 2 bits isn't really of any use.

maybe you should make sure that you don't divide by 0 when reseting your logic.

--

http://www.lateralsands.com/

 

[JTRAETS]

Sorry I mean 2 input busses and 1 output bus. I thought that the core was a known product.

Here you can find the datasheet:

http://www.xilinx.com/ipcenter/catalog/logicore/docs/pipediv_dsp.pdf

 

[VHDLguy]

Yeah I guess that was a dumb question on my behalf. Anyway, my comment still stands. the core might have a problem that it eventually gets into a bad state with lots of divide by zero's.

But another and probably more likely thought is your timing. Did your logic meet your clock speed?

One possibility is that after a long time your logic gets into some state which causes a different path to be active for your 2 input buses. If that different path doesn't meet timing then that would explain the incorrect behaviour.

--

http://www.lateralsands.com/

 

[JTRAETS]

I've tested the gated clock now and it solves the problem.

What timing is concerned, I'm not sure that can be the problem. The inputs are from accumulators (also cores) these are clocked also. When they give the outputs a counter waits for the division, and takes the quot and sends it to a FIFO.

I think that the problem is that the divider gets in a bad state when the FPGA is reloaded. It screws up after about 30 reloads. With the gated clock I reloaded it 54000 times and didn't fail. With the gated clock it doesn't start dividing directly after the load. This seems to be sufficient to keep it division correctly.

 

[VHDLguy]

interesting. So you wasn't just talking about reseting your logic, but rather reloading the fpga. Well good luck, sounds like you have something to work with anyway.

--

http://www.lateralsands.com/