Which is more efficient

[naraic]

Which of the following synthesises to more efficient code?

process(clk,rst)
begin
  if rst = '1' then
    ....
  elsif clk'event and clk = '1' then
    if a >= 16 then
      ....
    end if;
  end if;
end process;

OR

aGTEq16 <= '1' when a >= 16 else '0';

process(clk,rst)
begin
  if rst = '1' then
    ....
  elsif clk'event and clk = '1' then
    if aGTEq16 = '1' then
      ....
    end if;
  end if;
end process;

 

[berett]

It will be exactly the same - comparator with the output connected to the "enable" pin of the latched flip-flop

There is very little risk that the second solution would require additional inverter - if the flip-flop "enable" pin is active low. But then, if aGTEq16 was not used for anything else it would be surely and easily "optimised away".

Thus the second solution could add some tiny job for the synthesizer.
But who cares ...

 

[senjed]

I don't see much difference. I think he synthesizer will be able to optimize this amount of difference to the best. If not, of course the second is worse because of presence of 2 comparators (one equal to/greater than, the other equal to)

 

[naraic]

Ok. Say there were two processes

PR1: process(clk,rst)
begin
  if rst = '1' then
    ....
  elsif clk'event and clk = '1' then
    ....
    if a >= 16 then
      ....
    end if;
    ....
  end if;
end process;

PR2: process(clk,rst)
begin
  if rst = '1' then
    ....
  elsif clk'event and clk = '1' then
    ....
    if a >= 16 then
      ....
    end if;
    ....
  end if;
end process;

Would it be more efficient to use the line

aGTEq16 <= '1' when a >= 16 else '0';

as above, but in both processes.

This would replace two std_logic_vector comparisons with 1 std_logic_vector comparison and two std_logic comparisons.

 

[berett]

Well
in these circumstances the second solution could be better. Surely it would make the synthesis job easier. But now a good synthesis tool would "notice" that there are two identical comparators and eventually remove one of them.

Btw such problem could be considered as a test for optimisation capabilities of the synthesis soft. Me I am sure that any tool available on the market would pass it ))

rgds