Hello,
I am very new to VHDL and I am still learning but I have one very basic confusion. I have read that VHDL follows a top down approach to design generally and it is very convenient.
What I don't understand is suppose we make a VHDL program for some circuit, we may be starting from the behavioral description of the differnt modules and then define details. How do we know at which stage our code is completely synthesizable automatically to a gate level netlist. I mean if out code is very abstract I don't think that a synthesizer will be able to produce a gate netlist. So how do we know that this is the minimum details we need to give so now the code is synthesizable??
Please clarify anyone.
I am very new to VHDL and I am still learning but I have one very basic confusion. I have read that VHDL follows a top down approach to design generally and it is very convenient.
What I don't understand is suppose we make a VHDL program for some circuit, we may be starting from the behavioral description of the differnt modules and then define details. How do we know at which stage our code is completely synthesizable automatically to a gate level netlist. I mean if out code is very abstract I don't think that a synthesizer will be able to produce a gate netlist. So how do we know that this is the minimum details we need to give so now the code is synthesizable??
Please clarify anyone.