Vhld syntax problem? Beginners problem, vectors

[asc01001]

Hi!
I have a component UDP, wrritten in VHDL, se below. Then I have a an entity that looks something like this:
entyity User_Logic is
port(
Bus2IP_BE :in std_logic_vector(0 to 3);
);

component UDP_IP is
port(
rx_dv :in std_logic;
)
end component;

Now I want to connect those two signals, but the compiler do not like it. I got the "incompatible types" error.

How can I do to connect those two signals?
udp_pi: udp_ip port map(
rx_dv => Bus2IP_BE; --->?????? error
);

 

[VhdlForLife]

You're trying to connect a 1-bit signal to a 3-bit signal. That is not allowed! Did you forget the index of the bit you want connected to rx_dv?


[I'm assuming that there is more code between the entity and the component which you did not show.]