vhdl roms

[kasvela]

Hi everyone!

I know that vhdl can model a RAM memory, but I need a ROM memory, could I do something like a ROM memory?

I've been reading the datasheet of my cpld CY7C372i but it just says about logic blocks and macrocells, doesn´t tell me if I can´t do a ROM memory.

any help would be appreciated.

 

[yanant]

What level are you aiming to? For just simple design, I think the easiest way is design RAM first and create a wrapper entity that restricts direction of data flow (that's gonna be OUT port, NOT INOUT).

 

[HosseinMoradi]

Dear Kasvela,
in a process statement if you are using vhdl language you can defien a varity of constants in declaration part of process and then in it's body which is sensitive to OE pin or rd pin-that you've defined in the entity part-you use some addresses with if()statement or a case and then put those values of constant to your out port.

have a nice time;

Hossein Moradi