VHDL logic error

[byoung]

I am using the Xilinx WebPack synthesizer and I get an error with exit code 0006 from this piece of code -- All syntax is correct in the file. This code will compile with Figaro software from Atmel. Any suggestions? If you need a better description let em know, here is the snippet of code:


register_20: process (RESETn, waddr20, indata, reg20)
begin
if (RESETn = '0') then
reg20 <= &quot;0000&quot;;
elsif rising_edge (waddr20) then
reg20 <= indata(3 downto 0);
else
reg20 <= rst_conv;
end if;
end process register_20;

reset_conv: process (RDn, lataddr, rst_conv)
begin
if falling_edge (RDn) then
if (lataddr = &quot;00101&quot then
rst_conv(0) <= '0';
elsif (lataddr = &quot;01001&quot then
rst_conv(1) <= '0';
elsif (lataddr = &quot;01101&quot then
rst_conv(2) <= '0';
elsif (lataddr = &quot;10001&quot then
rst_conv(3) <= '0';
else
rst_conv <= reg20;
end if;
end if;
end process reset_conv;

 

[VhdlForLife]

byoung,

Most synthesizers are unable to synthesize else statements that come after an edge triggered condition like rising_edge or falling_edge because the else condition is true all the time except during the instant that the edge occurs. Some synthesizers just ignore this quietly, some give warnings and some actually generate an error statement.

VhdlForLife

 

[sunil287]

Hi,
In both the processes , one of the signal that is being driven is included in the sensitivity list. Try removing reg20 from the sensitivity list. And sensitivity list is also not updated properly. Signal rst_conv need to be included in the sensitivity list.