VHDL Homework problem

[flashpoint241]

Hi,

For school we have to make a little 'program' in vhdl. I never used VHDL before. Though I have quite a bit of experience in java,c and some other computer programming languages.

The program we have to make has two input signals: clock and input1; and one output signal. If the input signal is '1' (no matter if it's for less or more than one clock cycle) the output signal should be '1' for one clock cycle. As a hint is given that a SR-latch might be helpful.

I searched the internet for a SR-latch, since I don't have technical background I didn't know what it was. I still don't quite understand how a SR-latch can help me out. Could someone explain?
I think it should function as a memory when the input signal is '1'. So then I would have check the stored value on the beginning of every clock cycle and then decide what output signal should be. I've tried to play around with that (I had found a vhdl code for a sr-latch and used as component in my own code).
Another problem I ran into is howto make sure the output signal is '1' for one cycle even though the input might be '1' for 2 or more cycles? I was able to make something that would make the output signal '1' (for more clock cycles) when input was '1'.

I spent hours on this but I'm not able to figure out how to make it work.
So my main questions are
- How can a SR-latch be used in my case?
- Howto make sure the output signal is '1' for one cycle even though the input might be '1' for 2 or more cycles?


Any help would be gretly appreciated.

Marty.

 

[saiyijinprince]

An SR latch works like the following, you have the inputs S,R, and clk when
s=0, r=0, output = same as previous cycle
s=0, r=1, output = 0
s=1, r=0, output = 1
s=1, r=1, restricted

you can make the make the output change at the rising edge of the clk by making using the following test

if (clk'event and clk = '1') then ...