vhdl code find error

[helloperi]

hi all...
i just tried the fifo but it dint work out .....
i dont where i am stuck with...it is a 16 deep fifo with 8 bits.
the code is

library ieee;
use ieee.std_logic_1164.all;
use iee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity fifo is
port(reset:in std_logic;
clock:in std_logic;
writeenable:in std_logic;
readenable:in std_logic;
datain:in std_logic_vector(7 downto 0)
dataoutut std_logic_vector(7 downto 0));
end fifo;

Architecture a_fifo of fifo is
type stack is array(15 downto 0)of std_logic_vector(7 downto 0);
signal rdptr:std_logic_vector(3 downto 0)
signal wrtptr:std_logic_vector(3 downto 0)
signal value:stack;
signal fifoempty:bit;
signal fifofull:bit;
signal full:std_logic;
signal empty:std_logic;
signal notempty:std_logic;

begin
writerocess(clock)
begin
if((clock'event)and(clock='1')) then
if(reset='1') then
wrtptr="0000"
else if ((fifofull/='1')and(writenable='1')) then
value(conv_integer(wrtptr))<=datain;
wrtptr=wrtptr+'1';
end if;
end if;
end if;
end process write;

readrocess(clk)
begin
if((clock'event)and(clock='1')) then
if(reset='1') then
rdptr=&quot;0000&quot;
else if ((fifoempty/='1')and(readenable='1')) then
dataout<=value(conv_integer(rdptr));
rdptr=rdptr+'1';
end if;
end if;
end if;
end process write;

statusrocess(wrtptr,rdptr)
variable difference:std_logic_vector(3 downto 0);
begin
difference=wrtptr-rdptr;
if(difference)=&quot;0000&quot; then
fifoempty<='1';
elsif(difference)=&quot;1111&quot; then
fifofull<='1';
else
notempty<='1';
end if;
end process status;
end a_fifo


with this code i am able to get only the first data entry...the consecutive data entries are not able to be stored and read out...
i am not sure how far this code is correct...

it wuld be great help if u culd help me in this regard and make the fifo sucessful...
BYE.........

 

[RVSachin]

Hi,

This code has so many syntax errors...

The problem with your code at first glance is the empty and full flags always seem to stay at '1'.
One reason for this behaviour is the state of full and empty flags are unspecified when the difference = 0000 and &quot;1111&quot; respectively.

This causes read and write pointers not to be incremented. From the code, I assume, when fifo is empty, full cannot be asserted. So making fifofull = '0' and similarly when fifo is full, making fifoempty = '0'will solve the problem.

Hope this helps.

 

[berett]

... or just START the process STATUS with

BEGIN
fifoempty <='0';
fifofull <='0';
notempty <='0';

...

well according to the syntax errors
- there are several statements with = instead of <= or :=
- several ; missing
- the construction of the &quot;value&quot; register
is somewhat questionable from hardware point of view
but it shall simulate properly