vhdl code error

[picaso18]

hello

my project is synchronous communication between two 16v8. THe first 16v8 would take a signal from an 8 dill switch and using serial communication will communicate with the second one 16v8. From the second 16v8 a bcd decoder 74ls47 will be connected and then a 7 segment display.
So when switch 1 is turn on the number 1 will be shown, if swith 2 is turn on the number 2 will be shown etc. If two switches or more switches are turn on would show the E on the 7 segment display. A draft circuit diagram shown bellow.
The problem i have is that the second 16v8 will give me 8 outputs but the decoder 74ls47 has 4 inputs. I figure out, to add on the code after the serial to parallel communication to convert the outputs to BCD but it seems the compiler does not like it.
Here is my code and the error that gives me maybe someone can help me.

library ieee;
use ieee.std_logic_1164.all;

entity shift is
port(C, SI : in std_logic;
PO : out std_logic_vector(3 downto 0));
end shift;
architecture archi of shift is
signal tmp1: std_logic_vector(7 downto 0);
signal tmp2: std_logic_vector(3 downto 0);
begin
process (C)
begin
if (C'event and C='1') then --serial to parallel
tmp1 <= tmp1(6 downto 0)& SI;
if tmp1 = 10000011 then tmp2 <= 0001 ; --conversion to BCD
else if tmp1 = 10000101 then tmp2 <= 0010 ;
else if tmp1 = 10000111 then tmp2 <= 0011 ;
else if tmp1 = 10001001 then tmp2 <= 0100 ;
else if tmp1 = 10001011 then tmp2 <= 0101 ;
else if tmp1 = 10001101 then tmp2 <= 0110 ;
else if tmp1 = 10001111 then tmp2 <= 0111 ;
else if tmp1 = 10010001 then tmp2 <= 1000 ;
else tmp2 <= 1110;
end if;
end if;
end process ;
PO <= tmp2;
end archi;

The error is :
SIPO.vhd (line 33, col 16): (E56) Expected IF, but got PROCESS
Error occurred within 'IF' at line 27, column 11 in SIPO.vhd.
SIPO.vhd (line 33, col 16): (E10) Syntax error at/before reserved symbol 'process'.
SIPO.vhd (line 35, col 10): (E56) Expected IF, but got ARCHITECTURE NAME
SIPO.vhd (line 35, col 10): (ECool Syntax error: Can't use 'archi' (a ARCHITECTURE NAME) here.

It seems not to like the BCD conversion.

Thanks

 

[picaso18]

after some idea come to me i change my code to this

library ieee;
use ieee.std_logic_1164.all;

entity shift is
port(C, SI : in std_logic;
PO : out std_logic_vector(3 downto 0));
end shift;
architecture archi of shift is
signal tmp1: std_logic_vector(7 downto 0);
signal tmp2: std_logic_vector(3 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
tmp1 <= tmp1(6 downto 0)& SI;
case tmp1 is
when "00000000"=>tmp2<="0000";
When "00000001"=>tmp2<="0001";
When "00000010"=>tmp2<="0010";
When "00000011"=>tmp2<="0011";
When "00000100"=>tmp2<="0100";
When "00000101"=>tmp2<="0101";
When "00000110"=>tmp2<="0110";
When "00000111"=>tmp2<="0111";
When "00001000"=>tmp2<="1000";
When others=>tmp2<="1110";
End case;
end if;
end process ;
PO <= tmp2;
end archi;

but now the error is that the 16v8 does not have enough outputs which i can not undrestand because temp1 should not be an output since it is internal. the only output should be the PO.
what am i doing wrong here?