i am writing a for loop for a shift opperation. The opperation should shift a bit vector to the right V number of positions. The easiest way to shift that I know of(new to VHDL so may be missing some easier way) is to use a loop and shift each position once over whcih is done V times. whenever trying to write a for loop with a variable left bound I recieve an error telling me the left bound must be a constant....any suggestions? code snippet follows
entity RT1 is
port(a:in bit_vector(3 downto 0); v:in integer;out bit_vector(3 downto 0));
end;
architecture shift1 of RT1 is
signal temp:bit_vector(3 downto 0);
shared variable count:integer:=v;
begin
temp(0)<=a(0);
temp(1)<=a(1);
temp(2)<=a(2);
temp(3)<=a(3);
process (temp)
begin
loopy: for i in count downto 0
loop
temp(0)<=temp(1);
temp(1)<=temp(2);
temp(2)<=temp(3);
temp(3)<='0';
end loop;
end process;
end shift1;
i know there may be other errors but im simply worried about making it work for now before worrying about the details
entity RT1 is
port(a:in bit_vector(3 downto 0); v:in integer;out bit_vector(3 downto 0));
end;
architecture shift1 of RT1 is
signal temp:bit_vector(3 downto 0);
shared variable count:integer:=v;
begin
temp(0)<=a(0);
temp(1)<=a(1);
temp(2)<=a(2);
temp(3)<=a(3);
process (temp)
begin
loopy: for i in count downto 0
loop
temp(0)<=temp(1);
temp(1)<=temp(2);
temp(2)<=temp(3);
temp(3)<='0';
end loop;
end process;
end shift1;
i know there may be other errors but im simply worried about making it work for now before worrying about the details