dannybrowne
IS-IT--Management
Hi all,
I am new to VHDL and am trying to implement a buffer which takes std_logic inputs and puts them into a std_logic_array (my buffer) before output. I don't know how to put a series of bit values into an array and make them shift along to output.
I need to keep these values in array as I will need to read the contents of the array at different stages.
I would be very greatful of any help as im worried this might just ruin christmass for me!
Cheers danny
I am new to VHDL and am trying to implement a buffer which takes std_logic inputs and puts them into a std_logic_array (my buffer) before output. I don't know how to put a series of bit values into an array and make them shift along to output.
I need to keep these values in array as I will need to read the contents of the array at different stages.
I would be very greatful of any help as im worried this might just ruin christmass for me!
Cheers danny