Unsupported Clock statement

[annadorian]

Hi all,

I have a problem and I can not find a solution So I have a code which I could simulate without any problems but I can not sintethize it with Xilinx Project Navigator! I realized a state automaton and it has to work on both edges of signals but in Xilinx I have error "Unsupported Clock statement" for the first line of the processes because XST does not support the use of a complex condition check inside a process block in VHDL. How could I solve my problem?

process(clk, rst_n, init_done, sys_clk_out, sdr_clk)
begin
if (clk'event and clk = '1') or (sys_clk_out'event) or (sdr_clk'event) then
case (current_state) is
when rst_state =>
--some code
when init_state =>
--some code
when wr_state =>
--some code
--...some other states
when end_state =>
--some code
end case;

end if;

end process;

Thanks in advance.

 

[jeandelfrigo]

Annadorian,

Your code does not synthesize because it would result in registers or flip flops with three clock inputs.
These do not exist.

To fix it you will need to write three seperate processes, one for each clock. Make sure however you assign a signal or port only once (= in one process).
So you will need to seperate your assignments (= the some code). All signals/ports that should change synchronous to Clk should be assigned in the process with clk and the same for the other signals.


Just out of curiousity, what are you trying to make?

Regards
jeandelfrigo

 

[annadorian]

Thanks for your answer. I try to synthesize DDR SDRAM Controller but it's not going very easy. Unfortunately I could not separate my state automaton to several processes But I would try to find a way around.

 

[jeandelfrigo]

annadorian,

Nice work, nice challenge designing DDR controllers.
Do you have a lot of VHDL and or hardware design expirience?

This is not an easy design. Is it DDR1 or DDR2? At what frequencies are you thinking of running the controller?

I am asking this because it is very relevant for the way you design, the way you write your code.

I noticed you are using XST, do you have access to the Xilinx IP cores? They have some DDR cores and reference designs. It's allways handy to take a peak in there if possible.

Also keep the datasheet of your DDR SDRAM close at hand when writing the code.

I wish you a lot of fun and good luck.

Best regards,
Jan