annadorian
Programmer
Hi all,
I have a problem and I can not find a solution So I have a code which I could simulate without any problems but I can not sintethize it with Xilinx Project Navigator! I realized a state automaton and it has to work on both edges of signals but in Xilinx I have error "Unsupported Clock statement" for the first line of the processes because XST does not support the use of a complex condition check inside a process block in VHDL. How could I solve my problem?
process(clk, rst_n, init_done, sys_clk_out, sdr_clk)
begin
if (clk'event and clk = '1') or (sys_clk_out'event) or (sdr_clk'event) then
case (current_state) is
when rst_state =>
--some code
when init_state =>
--some code
when wr_state =>
--some code
--...some other states
when end_state =>
--some code
end case;
end if;
end process;
Thanks in advance.
I have a problem and I can not find a solution So I have a code which I could simulate without any problems but I can not sintethize it with Xilinx Project Navigator! I realized a state automaton and it has to work on both edges of signals but in Xilinx I have error "Unsupported Clock statement" for the first line of the processes because XST does not support the use of a complex condition check inside a process block in VHDL. How could I solve my problem?
process(clk, rst_n, init_done, sys_clk_out, sdr_clk)
begin
if (clk'event and clk = '1') or (sys_clk_out'event) or (sdr_clk'event) then
case (current_state) is
when rst_state =>
--some code
when init_state =>
--some code
when wr_state =>
--some code
--...some other states
when end_state =>
--some code
end case;
end if;
end process;
Thanks in advance.