test bench in VHDL

[byadeg]

hi,

Can any one help me with this.....

What is the equivalent code in a VHDL ( for the purpose of writing a test bench) for this command in the Modelsim command promt..

VSIM>force -freeze /DATA/ 10101100 0 -cancel 50

the DATA here is a INOUT type. I want it to be in the VHDL like this....

DATA<=&quot;10101100&quot; ;
wait for 50 ns;

What should be here now in VHDL to cancel the data I loaded after 50 ns? What is the eqivalent for &quot;-cancel 50&quot; in VHDL

Please help me....Thank you!

 

[VhdlForLife]

DATA <= (OTHERS => 'Z');