Simple "if" costs 72MB memory???

[PeggyYao]

Hi, all,

I just started playing around with Xilinx ISE 6.2i. The logic of my testing VHDL code is very simple: 1 if statement and 2 assignment statements. However, the "Place & Route" reports my that the Peak Memory Usage is 72 MB!

The "stopwatch" tutorial provided by Xilinx has more complicated logic, but only has peak memory usage of 56MB...

Memory usage is a major limitation of FPGA, isn't it? Can anybody tell me some tips on how to avoid large memory usage?

The following is the code of the simple logic which still costs 72 MB, for your reference.

entity try is
Port ( A : in bit;
B : in bit;
C : in bit;
D : out bit);
end try;

architecture Behavioral of try is
begin
process (A)
begin
if A = '1' then
D <= B;
else
D <= C;
end if;
end process;
end Behavioral;

 

[VHDLguy]

are you talking about you CPU memory usage while synthesizing, or the amount of resources used on the FPGA. The amount of resouces on an FPGA are a limitation. but it doesn't matter how much CPU memory you use while synthesizing - as long as its not so big that it causes the synthesis to take forever or not work at all, but then we are talking in the gigabytes. Synthesis and simulation can eat up the memory.

I don't know why the difference, maybe you used difference packages or something like that (try using std_logic rather than bit - its more standard than using bit, although I would think it would use even more CPU memory).

Your FPGA resources for this logic would be VERY small.

If you got the 72Mb from some xilinx report, post the information and I can explain what to look at.

--

http://www.lateralsands.com/

 

[PeggyYao]

Thank you for your reply! I am a new user to Xilinx ISE tool, also a novice at programming in VHDL...

There are several reports, such as Synthesis Report, Translation Report, Map Report and Place & Route Report. Which one shall I look at if I want to know the utilization of the FPGA?

The following is the Map Report in Implement Design. Could you tell me what does "slice", "LUT" and "IOB" mean? The last line shows the "peak memory usage" that I mentioned last time.

Thank you very much in advance!

Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of 4 input LUTs: 1 out of 10,240 1%
Logic Distribution:
Number of occupied Slices: 1 out of 5,120 1%
Number of Slices containing only related logic: 1 out of 1 100%
Number of Slices containing unrelated logic: 0 out of 1 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 1 out of 10,240 1%

Number of bonded IOBs: 4 out of 172 2%

Total equivalent gate count for design: 6
Additional JTAG gate count for IOBs: 192
Peak Memory Usage: 80 MB

 

[PeggyYao]

By the way, I've tried to modify "bit" to "STD_LOGIC". The Map Report is identical as previous.

The following is part of Place & Route Report.

Device utilization summary:

Number of External IOBs 4 out of 172 2%
Number of LOCed External IOBs 0 out of 4 0%
Number of SLICEs 1 out of 5120 1%

 

[VHDLguy]

IOB - IO Block
LUT - Look Up Table

FPGA companies are pretty good about putting ltos of useful info on their websites. For example the Xilinx spartan II datasheet

http://direct.xilinx.com/bvdocs/publications/ds001.pdf

If you look through that you can see what a slice, a CLB and an IOB is. I would recommend reading the architectural description section. Especially the configurable logic block section and Input/Output Block section of that datasheet. It pretty much applies to all devices with some small differences, so you can either read that one, or look up your particular device.

So you are using 4 (of 172 available) pins and 1% of your CLB/LC/LUT/Slices/WhatEverYouWantToCallThem resources.
There is no mention of memory blocks that you are using, so either your device has none, or more likely it just doens't tell you when you are not using any of them.

90M is you CPU usage, there is no way that your device has anything near that. FPGA internal RAM is usually measured in the K bytes and only in small M bytes for the newest largest devices.

--

http://www.lateralsands.com/

 

[VHDLguy]

hmmm actually I meant RAM is measured in k bits and now M bits not bytes.

--

http://www.lateralsands.com/

 

[jeandelfrigo]

PeggyYao,

The VHDL code you wrote is a simple multiplexer.
This will require only 1 Look up table of the FPGA.
The more VHDL you write the more you will get expierience in resources your code eats.

As mentioned above the memory usage is the peak of RAM memory used by the ISE tool for performing a certain step in the design flow.

Most synthesis and vendor tools for Hardware design tend to use a lot of PC resources.

Normally the less memory you have in in your PC and the complexer your design gets and the larger the device the more time it will take to generate your hex or bitfile.
Even if you only have 128 MB of RAM and the tool requires 200MB it will start virtual memory on the hard disk.

As long as your PC meets the minimum system requirements for the tool you should have no problems.

Regards
jeandelfrigo