signal names within loops

[me360]

is it possible to, in a loop, have the names of signals be changed as the iterator changes.. for example if i have a loop from 0 to 3 can i have a 4 seperate signals named out0, out1, out2, out3 each be assigned in the loop? (each out would itself be a vector so i cannot just make a vector called out)

 

[ahedin]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity temp2 is
port (RST : in std_logic;
CLK : in std_logic;
Bin : in std_logic_vector(3 downto 0));
end temp2;


architecture sim of temp2 is

--I don't know how to make the std_logic_vector an arbitrary length
--without using pointers(which is not synthesizable ... yet)
type slv_array is array (natural range <>) of std_logic_vector(3 downto 0);

signal matrix : slv_array(4 downto 0);

signal vout : std_logic_vector(3 downto 0);

begin

main : process(RST,CLK)
begin
if RST = '1' then
vout <= &quot;0000&quot;;
elsif rising_edge(CLK) then
for i in 0 to 3 loop
vout(i) <= Bin(i);
end loop;
end if;
end process;

main2 : process(RST,CLK)
begin
if RST = '1' then
matrix <= (others => (others => '0'));
elsif rising_edge(CLK) then
for i in matrix'range loop
matrix(i) <= matrix(i) + i + 1;
end loop;
end if;
end process;

end sim;