shared variable-memory modeling

[hnew]

I am modeling a large DRAM using access variable. Functions for uploading memory from a file and downloading memory to a file are also needed. These functions will be shared by a number of processes in different VHDL files. The memory controller will issue the regular memory read/write accesses. To do that, I declare the memory as shared variables in the package. However, since the simulator is using multi-threaded processes, the memory was corrupted due to the concurrent accesses of the variables by processes. In VHDL-2001, there is protected type to allow muture exclusive use of the variable. However, protected types cannot be used by elements of the composite type, nor as types designated by the access type. I am not so sure what to do. Any ideas?

Thanks in advance.

 

[stevieblunder]

How about a time division mux schedule, at least for writing to RAM.

Steve