same frequency but different duty cycle

[spidermanvenom]

To everyone,

I am programing a VHDL for PLD. Does anyone knows the code or algorithm of generating a new clock with a different duty cycle from a given clock. (For example, the given clock 50MHz has a 50% duty cycle, the output clock should have 50 MHz too but with 85% duty cycle.

Thanks!

 

[VHDLguy]

Well the simple and 'ideal' way to do it is to multiply the clock and then count a number of clocks to get to your required duty cycle.

For example 5/6 = .8333 or 83.3% duty. So multiply clock by 6 then count 5 clocks, invert, count 1 clock invert, 5 clocks invert etc.

If you want to get exactly 85% you will either need to multiply by 10 then use rising and falling edges of clocks to count 8.5 and 1.5. Or multiply by 20 and count 3, 17, 3, 17 etc.


I say 'ideal' because this may not be an option.
1. If your FPGA/PLD does not have a PLL/DLL/DCM then you will have a hard time multying the clock
2. Your device may not be able to produce a multiplied clock that fast (for example at 20 x 50Mhz you are out of luck).

Finally. Are you planning on using this clock as an internal logic clock? My assumption is that this clock is just an output of the FPGA/PLD that is used by some other chip. If so watch out for jitter.

If you do plan on using it internally then you will need to make sure that your logic runs at the period of the lowest duty cycle, not at the clock rate. For example at 50Mhz, 85%... That would really be a clock period of 3ns * 2 or 166Mhz. And you would have to account for a large amount of jitter etc on your new clock also.


--

http://www.lateralsands.com/

 

[spidermanvenom]

Thanks!

I will try your ideal suggestion. I will search for the PLL of the PLD I'm using. I'm going to use it internally not an output of PLD. I'm just a beginner programmer of VHDL that's why I'm asking for somebody's help. Thanks again!

 

[VHDLguy]

What speed clock are you likely to have?

 

[VHDLguy]

Oh, and out of curiosity, why the 85% duty cycle?
The only thing I can think of is that it somehow helps you look at what is happening on an input, and maybe you are better to do it another way.

 

[spidermanvenom]

Here are the clock signals I need to get from a VHDL program. That's the problem, how can I generate those clock signals from inputclk only.


_____________________ ______
inputclk => ____| |______________|

internal clock signals:
______ ______
clk0 => ____| |_____________________________| |
______
clk1 => ________ | |______________________________
______
clk2 => ____________ | |_________________________
______
clk3 => ___________________| |____________________
______
clk4 => ________________________| |_______________
______
clk5 => _____________________________| |__________
______
clk6 => __________________________________| |_____

 

[berett]

So ... let me say ... now ...

Now it is clear that the first VHDLguys reply is just t what you need
I.e.:

1. You generate the 7 times faster clock using the PLL or other magic "out of digital world" device
2. You make a 0 to 6 counter with this fast clock
3. You implement a MUX for each of the outgoing clocks,
just e.g.

clk_0 <= '1' when counter= &quot;000&quot; else '0';
clk_1<= '1' when counter= &quot;001&quot; else '0';

-- etc

3a. Or you consider only 1 mux - for clk_0 and then series of 6 registers for shifting the other clocks (regs are clocked by the faster clock). Depends on ... below

The only problem seems the 350 MHz operating frequency for the stuff. It is going to be rather expensive FPGA. And/or no other, really complicated logic shall be placed inside together with your clocking widget.

Maybe we shall ask now - do you really need these funny clocks and why )) who knows ... ?

rgds
Berett

P.S. Sorry VHDLguy - couldn't resist

 

[spidermanvenom]

Thanks for the comment.

If you know about the LVDS Receiver, I need LVDS Receiver inside of PLD. As a beginner programmer of VHDL, I have an idea, but the problem is implementation. I don't know how can I put in on code.

Thanks again!

 

[VHDLguy]

Berett, No problem, I was on vacation, so it was timely of you to not resist.

spidermanvenom... You will need to instantiate a LVDS IO from your FPGA vendor's libraries. I am not 100% sure (haven't not used them before) if they can be found in things like the Xilinx Architecture Wizard, or maybe they just have a library with all different things you can use within your code.

Vendor's websites are usually pretty good for this kind of thing - search for &quot;implementing LBDS&quot; in their knowledge base.

--

http://www.lateralsands.com/